{"id":2060623,"url":"https://alion.io/job/synopsys-fpga-design-and-test-engineer-sr-staff-18509","title":"FPGA Design and Test Engineer, Sr Staff - 18509","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":98,"open_postings":65,"ghost_share":0.062,"stale_share":0,"repost_share":0.231,"time_to_fill_p50_days":17,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":156000,"max_usd":288000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-08T01:44:10Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-11-02T16:27:26Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years turning ASIC designs into working FPGA prototypes, and you know the difference between RTL that compiles and RTL that actually runs reliably across multiple FPGAs at speed. The challenge excites you: partitioning a design that was never meant to be split, closing timing on a path that crosses three SLRs, or debugging a reset issue that only shows up in hardware after two hours of runtime.\nYou are equally comfortable writing SystemVerilog that synthesizes cleanly and Python scripts that automate the tedious parts of your workflow. When a bring-up fails, you reach for the logic analyzer, the scope, and the source code in that order, and you do not stop until you understand why. You have learned that production-quality tools matter as much as production-quality RTL, and you build both.\nMulti-FPGA systems do not intimidate you. Clock domain crossings, inter-FPGA communication, resource utilization analysis, these are problems you have solved before, and you know how to solve them again under new constraints. You work well with hardware teams, software teams, and manufacturing teams because you understand that your prototype is only useful if it helps someone else move forward.\nAt Synopsys, you will work on HAPS prototyping platforms that enable real customer designs to run before silicon exists. The problems are hard, the systems are real, and what you build will directly affect how quickly our customers can validate their next chip.\nWhat You'll Be Doing\nDevelop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges\nOwn the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices\nDrive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues\nDevelop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins\nBuild and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries\nDebug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers\nCollaborate with architecture, hardware, software, manufacturing, and verification teams to deliver prototyping solutions from concept through production deployment\nThe Impact You Will Have\nEnable customer ASIC designs to run on HAPS platforms months before silicon is available, directly accelerating their validation schedules and reducing risk\nDeliver FPGA implementations that close timing, meet performance targets, and run reliably in production test environments, reducing debug cycles and improving product quality\nBuild automation tools and workflows that make FPGA bring-up faster and more repeatable for the entire HAPS Production Test Team\nSolve complex multi-FPGA partitioning and communication challenges that unlock prototyping for designs that would otherwise be too large or too fast for a single device\nIdentify and resolve signal integrity, timing, and hardware issues that would otherwise delay product releases or cause field failures\nCreate test frameworks and validation infrastructure that catch issues early and give manufacturing teams confidence in what they are shipping\nContribute technical expertise and design documentation that raises the bar for how the team approaches FPGA development, bring-up, and production test\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field\n10+ years of hands-on FPGA and RTL design experience\nExpert-level proficiency in SystemVerilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis\nExtensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion\nStrong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug utilities, and engineering tools\nProficiency using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and multimeters to debug and validate hardware systems\nExperience with signal integrity characterization, PRBS testing, eye diagram analysis, jitter measurement, and link margining is a strong plus\nWho You Are\nWhen a prototype fails bring-up, you methodically work through the possibilities, RTL bug, clock issue, FPGA tool problem, hardware fault, and you do not assume it is someone else's domain until you have ruled out your own\nYou write Python scripts and C/C++ tools that other engineers actually use because you care about usability, error handling, and documentation, not just getting something to run once on your machine\nYou can explain a complex multi-FPGA partitioning tradeoff to a hardware engineer or a software validation lead in terms they understand, without losing the technical nuance that matters\nYou stay current with FPGA technology, Vivado features, and AMD/Xilinx architecture updates because you know that a new tool capability or device feature can sometimes unlock a solution that was not possible six months ago\nYou are comfortable working across teams, whether that means reviewing schematics with hardware engineers, debugging test failures with manufacturing, or aligning on requirements with architecture and verification teams\nThe Team You'll Be Part Of\nYou will join the HAPS Production Test Team, a group responsible for enabling customer ASIC designs on Synopsys HAPS prototyping platforms and ensuring those systems are validated, tested, and ready for production deployment. Your recruiter will share more about the team structure and mission during the interview process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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