{"id":1651989,"url":"https://alion.io/job/synopsys-hardware-validation-engineer-sr-staff-18755","title":"Hardware Validation Engineer, Sr Staff - 18755","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":90,"ghost_share":0.033,"stale_share":0,"repost_share":0.144,"time_to_fill_p50_days":10,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":216000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":23},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false}],"status":"live","first_seen_at":"2026-10-02T00:31:24Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-02T00:31:24Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years turning design files into real boards that work, not just pass DRC, actually work when you power them up and start probing signals. You know that a clean schematic means nothing if the layout introduces crosstalk that kills your eye diagram.\nYou live in the space between design intent and physical reality. When a signal integrity simulation says one thing and the scope says another, you do not pick a side, you figure out which assumption was wrong. You have routed enough high-speed interfaces to know that JTAG chains fail for predictable reasons and that S-parameters tell a story if you know how to read them.\nAt Synopsys, you will validate memory interface IP where the margin between working silicon and a customer escalation is measured in picoseconds, and your board-level work is what closes that gap.\nWhat You'll Be Doing\nDesign, layout, and validate PCBs in Cadence Allegro for memory interface IP characterization and customer reference designs\nAnalyze high-speed signal behavior using S-parameters, eye diagrams, and crosstalk simulations to ensure signal integrity across multi-gigabit interfaces\nRoute and validate communication interfaces including JTAG, I2C, and other low-speed control planes with attention to noise immunity and timing margins\nDebug board-level issues using logic analyzers, oscilloscopes, and protocol analyzers to isolate failures across silicon, firmware, layout, and test setup\nReview design files and layout with cross-functional teams, teaching best practices for routing, decoupling, and design rule adherence\nInterpret simulation waveforms from SPICE, IBIS, and channel analysis tools to validate analog and mixed-signal circuit performance\nDrive root cause analysis on validation failures, determining whether issues stem from silicon behavior, board design, or environmental factors\nThe Impact You Will Have\nYour board designs will serve as the validation platform for Synopsys memory IP used in customer production deployments across automotive, mobile, and data center applications\nThe signal integrity work you do will directly inform design guidelines that prevent customer respins and reduce time to market\nYour debug findings will feed back into silicon design teams, closing the loop between simulated and measured performance\nThe review practices you establish will raise the quality bar for how the team evaluates layout and catches issues before boards are fabricated\nYour ability to isolate failures quickly will accelerate bring-up schedules and get IP into customer hands faster\nThe reference designs you validate will become the foundation for how customers integrate Synopsys IP into their own systems\nYour mentorship will build the next generation of validation engineers who understand the full stack from transistor to trace\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering, Electronics Engineering, or equivalent hands-on experience\n6-8+ years of Hardware design and validation experience with a focus on high-speed digital and mixed-signal systems\nExpert-level proficiency in Cadence Allegro for schematic capture, PCB layout, and constraint-driven design\nDeep understanding of signal integrity concepts including S-parameters, impedance control, crosstalk, intersymbol interference, and return loss\nStrong knowledge of analog IC circuit design and the ability to analyze SPICE simulation waveforms and correlate them to measured behavior\nHands-on experience debugging hardware using logic analyzers, oscilloscopes, VNAs, spectrum analyzers, protocol analyzers, and other bench instrumentation\nExperience with communication interfaces such as JTAG, I2C, SPI, and UART, including routing best practices and protocol-level debug\nKnowledge of PCB stack-up design and high-speed materials.\nWho You Are\nYou drive complex technical problems independently across multiple disciplines without waiting for direction\nYou diagnose whether a failure is silicon, firmware, board, or test setup and make the call quickly\nYou translate technical findings into clear recommendations that design, firmware, and customer teams can act on\nYou mentor junior engineers through their first characterization projects without taking over the work\nYou push back when validation coverage is thin or root cause stops at correlation instead of causation\nThe Team You'll Be Part Of\nYou will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":5888,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-02T00:31:24Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":10,"reasons":["conf:5","velocity","win:early","comp:brand"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-hardware-validation-engineer-sr-staff-18755","json_url":"https://alion.io/job/synopsys-hardware-validation-engineer-sr-staff-18755.json","meta":{"generated_at":"2026-10-03T03:18:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3021,"day_limit":5000,"remaining_today":1979,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}