{"id":3133557,"url":"https://alion.io/job/synopsys-intern-technical-engineering-19333","title":"Intern (Technical-Engineering) - 19333","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":77,"ghost_share":0.039,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":15,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Da Nang, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Unix","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Git","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-23T04:49:10Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-25T06:47:37Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nTechnical Engineering Intern- Design Verification Internship\nIntroduction\nWe Are:Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.\nInternship Experience:At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide-and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!\nMission Statement:Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive-both at work and beyond.\nWhat You'll Be Doing\nAs a Design Verification Intern, you will play an important role in supporting the development of high-quality semiconductor IP and EDA solutions by assisting with the verification of complex digital designs. The core purpose of this team is to ensure the quality, functionality, and reliability of advanced semiconductor IP and SoC solutions through comprehensive design verification. Your responsibilities will include:\nDeveloping and Executing Verification Testcases:Create comprehensive testcases using SystemVerilog and UVM methodologies to verify complex digital designs, including constrained-random testing scenarios and functional coverage analysis.\nSimulation and Debugging:Run simulations using industry-standard EDA tools, analyze results, and debug design issues to identify and resolve functional problems, contributing to improved product quality and reliability.\nTestbench Development:Assist in building and enhancing verification environments and testbenches, implementing verification IP (VIP) for various protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, and other industry-standard interfaces.\nCoverage-Driven Verification:Develop functional coverage models and analyze coverage metrics to ensure comprehensive verification of design features, helping to reduce design risk and accelerate project execution.\nCollaboration and Learning:Work closely with design, verification, and validation teams to understand product architecture, verification flows, and methodologies, while contributing fresh perspectives and innovative solutions to technical challenges.\nWhat You'll Need\nRequired Qualifications:\nCurrently pursuing a degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related technical discipline.\nBasic understanding of Digital Design fundamentals, including combinational/sequential logic, finite state machines (FSM), clocking, and reset concepts.\nKnowledge of Verilog/SystemVerilogfor RTL design and verification.\nFamiliarity with design verification methodologies, preferably UVM (Universal Verification Methodology) concepts.\nUnderstanding of verification techniquessuch as testcase development, constrained-random testing, functional coverage, and debugging.\nFamiliarity with Linux/Unix operating environmentsand simulation tools.\nStrong analytical and problem-solving skillswith the ability to investigate and debug complex technical issues.\nGood communication skills, both written and verbal, to effectively collaborate with design, verification, and validation teams.\nAbility to work independentlyas well as in a team-oriented environment.\nPreferred Qualifications:\nExperience with assertion-based verification (SVA)and coverage-driven verification techniques.\nKnowledge of scripting languagessuch as Python, Perl, Shell, or TCL.\nFamiliarity with version control systemslike Git.\nUnderstanding ofindustry-standard protocolssuch as PCIe, UCIe, DDR, AXI, APB, AHB, SPI, I2C, or UART.\nExperience with FPGAor hardware verification projects.\nKey Program Facts\nProgram Length:December 2026 - May 2027 (6 months)\nLocation:Vietnam (VN10)\nWorking Model:Onsite\nFull-Time/Part-Time:Full-Time\nStart Date:December 2026\nEqual Opportunity Statement\nSynopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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