{"id":1311343,"url":"https://alion.io/job/synopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452","title":"IP Implementation & Physical Design Engineer ( Serdes Subsystem) - 18452","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":89,"ghost_share":0.034,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":11,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":42000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1605},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Edge AI","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Unix","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-12T19:36:21Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":16},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years turning RTL into silicon that actually worksat 5GHz, not just in simulation, but in the lab when the first testchipcomes back. You know that a poorly planned power grid or a clock tree that looked fine in tool reports can kill a tapeoutthree weeks before the deadline, and you are the kind of engineer who sees those problems during floorplanning, not during signoff.\nYou are comfortable living in the Synopsys EDA toolchain, moving between Fusion Compiler for place and route, PrimeTimefor timing closure, and StarRCfor extraction without losing sight of what you are building: a high-speed interface IP that has to meet setup, hold, power, and area targets simultaneously. When a timing path fails by 200ps at a corner you were not expecting, you debug the netlist, check the constraints, talk to the RTL team if needed, and find the fix.\nYou care about methodology because a good flow means you iterate faster and catch issues earlier. Writing a TCL script that automates floorplan generation is not overhead,it is how you scale. At Synopsys, you will work on interface IP and testchipsthat go into AI accelerators, autonomous vehicle SoCs, and 5G infrastructure at 7nm, 5nm, and 3nm nodes.\nWhat You'll Be Doing\nDrive complete digital implementation from RTL to GDS for high-speed interface IPs including Serdes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes\nExecute synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, and physical verification using Synopsys EDA tools\nPerform static timing analysis and close timing across multiple process corners, voltages, and operating modes\nRun EMIR signoff, analyze IR drop and electromigration, and iterate on power grid design to ensure reliable silicon operation\nBuild physical design methodologies and automation scripts using TCL, Python, Perl, and Make to improve efficiency across projects\nCollaborate with RTL designers, verification teams, product engineers, and customers to ensure timely delivery and resolve technical issues\nProvide technical support to customers during IP integration and debug design issues as they arise\nThe Impact You Will Have\nEnable cutting-edge AI, autonomous vehicle, high-performance compute, cloud, 5G, and IoT applications by delivering silicon-proven interface IP\nAccelerate time to market for Synopsys customers by providing production-ready IP and testchipsthat integrate cleanly into advanced SoC designs\nImprove physical design quality across the IP portfolio by creating reusable methodologies and automation that scale across projects and process nodes\nReduce design iteration cycles and signoff risk by catching timing, power, and physical issues early through disciplined analysis\nStrengthen customer confidence by delivering IP that works the first time in silicon and providing responsive technical support\nContribute to Synopsys leadership in the interface IP market by pushing the boundaries of what is possible at 3nm and beyond\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science\n5+ years of hands-on experience in ASIC physical implementation, specifically RTL to GDS flows using industry-standard EDA tools\nDeep understanding of IC design fundamentals, physical implementation flows, and signoff methodologies for deep submicron designs\nProficiency with industry-standard data formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPF, and SPEF\nStrong scripting skills in TCL, Python, Perl, Unix Shell, and Make for automation and flow development\nSolid written and verbal communication skills in English for technical documentation and cross-functional collaboration\nExperience with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, or StarRCis a strong plus\nWho You Are\nYou can look at a floorplan and immediately spot the congestion hotspot or the power domain that is going to cause problems three steps downstream\nWhen a design fails timing by 500ps after routing, you step back, check the constraints, review the clock architecture, and figure out what actually needsto change\nYou are comfortable explaining why a particular timing closure strategy will or will not work to product managers and IP architects without getting lost in tool settings\nYou write automation scripts that other engineers can actually readand modify six months later\nYou treat deadlines seriously, but you know when to flag a risk early rather than hoping it resolves itself during the next iteration\nThe Team You'll Be Part Of\nYou will join the Digital Implementation team, a group responsible for delivering high-speed, silicon-proven interface IP, testchips, and subsystem solutions at the latest process nodes. The team works on advanced technology supporting AI, autonomous vehicles, high-performance compute, cloud infrastructure, 5G mobile, and IoT applications.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5965,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"visa":[],"liveness":{"score":37,"band":"fade","label":"Fading","p_open":1,"p_active":0.666,"p_room":0.55,"age_days":15,"expected_fill_days":11,"reasons":["conf:3","velocity","win:tail","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452","json_url":"https://alion.io/job/synopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452.json","meta":{"generated_at":"2026-10-12T20:37:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33516,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-ip-implementation-physical-design-engineer-serdes-subsystem-18452"}]}