{"id":1887388,"url":"https://alion.io/job/synopsys-layout-design-engineer-18419","title":"Layout Design, Engineer - 18419","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":84,"ghost_share":0.036,"stale_share":0,"repost_share":0.179,"time_to_fill_p50_days":11,"computed_at":"2026-10-07T05:47:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Da Nang, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":12500,"max_usd":30000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":524},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Custom Compiler","optional":false}],"status":"live","first_seen_at":"2026-10-05T03:17:14Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-08T01:44:10Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nAlternate Job Titles\nCustom Layout Engineer\nIC Layout Designer\nVLSI Layout Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent enough time in layout to know that the best designs do not happen by accident. They happen when someone understands what the circuit is trying to do and uses that understanding to make better placement, routing, and spacing decisions. You think about device matching, current density, and parasitic impact before you draw the first rectangle, not after DRC fails.\nYou are the kind of engineer who looks at a schematic and sees the layout challenges before anyone asks. FinFET design rules do not scare you, they shape how you think about structure and symmetry. When LVS breaks, you do not guess. You trace nets, check hierarchies, and find the actual mismatch. Debugging does not frustrate you, it is part of the craft. You know that clean DRC and LVS are table stakes, the real work is making sure the layout supports the electrical intent without introducing problems three months later during characterization.\nAt Synopsys, you will work on memory and standard cell layouts that ship in real products, and the decisions you make in Custom Compiler will show up in silicon across multiple process nodes.\nWhat You'll Be Doing\nDesign custom layouts for memory and standard cell IP using Custom Compiler, translating circuit schematics into physical structures that meet performance, power, and area targets\nRun and debug physical verification flows using ICV or Calibre, resolving DRC, LVS, and ERC violations with an understanding of root cause\nAnalyze layout parasitics and perform EMIR checks to ensure your designs meet electrical and reliability requirements\nCollaborate with circuit designers to understand design intent, device sizing, and matching requirements, then implement layouts that preserve those goals\nBuild and refine layout cells that integrate cleanly into larger IP blocks, ensuring hierarchy, pin placement, and routing consistency\nSupport bring-up and characterization activities by investigating layout-related issues flagged during post-silicon validation\nThe Impact You Will Have\nDeliver memory and standard cell layouts that meet aggressive performance, power, and area targets for leading-edge semiconductor markets\nImprove silicon quality and yield by catching layout-induced issues early, reducing the risk of costly respins\nAccelerate project schedules by automating layout tasks and verification flows\nRaise the bar for layout quality across the team by sharing best practices and debugging techniques\nEnable faster design iteration cycles by delivering clean, well-structured layouts that integrate smoothly with downstream teams\nHelp define layout methodologies that scale across multiple process nodes and design families\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field\n2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design\nStrong knowledge of MOSFET and FinFET device characteristics, P-N junctions, resistors, capacitors, antenna effects, and EMIR analysis\nProficiency with Custom Compiler and physical verification using ICV, Calibre, or similar platforms\nSolid skills in DRC, LVS, and ERC debugging, with the ability to trace issues back to layout or netlist source\nWho You Are\nYou approach layout with a designer's mindset, understanding circuit intent and using that knowledge to make better layout decisions\nYou do not stop at clean DRC and LVS. You ask whether the layout actually supports the electrical performance the circuit needs\nYou are comfortable working across tools and flows, moving between Custom Compiler, verification platforms, and parasitic extraction without losing momentum\nYou communicate clearly with circuit designers and verification engineers, translating layout constraints into terms that help the team make better tradeoffs\nThe Team You'll Be Part Of\nYou will join a global engineering team focused on custom layout and physical design for memory and standard cell IP. The team works closely with circuit designers, verification engineers, and process technology partners to deliver high-performance layouts for advanced FinFET nodes.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5270,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-05T03:17:14Z"}],"visa":[],"liveness":{"score":85,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.851,"p_room":1,"age_days":2,"expected_fill_days":11,"reasons":["conf:0","velocity","win:early","comp:junior,brand"],"computed_at":"2026-10-07T05:47:15Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-layout-design-engineer-18419","json_url":"https://alion.io/job/synopsys-layout-design-engineer-18419.json","meta":{"generated_at":"2026-10-08T02:30:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4326,"day_limit":5000,"remaining_today":674,"minute_limit":60,"resets_at":"2026-10-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-layout-design-engineer-18419"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-layout-design-engineer-18419"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-layout-design-engineer-18419"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-layout-design-engineer-18419\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-layout-design-engineer-18419"}]}