{"id":4013358,"url":"https://alion.io/job/synopsys-layout-design-sr-engineer-19417","title":"Layout Design, Sr Engineer - 19417","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yerevan, Armenia"],"countries":["AM"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Synopsys Custom Compiler","optional":false}],"status":"live","first_seen_at":"2026-11-10T11:17:58Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-11T12:17:35Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent real time in layout tools, not just opening Virtuoso but actually building memory cells, bitcells, and arrays that have to meet density, performance, and reliability targets in nodes where a few nanometers matter. You understand that SRAM layout is not just drawing rectangles, it is about symmetry, matching, minimizing parasitic capacitance, and making sure the circuit your designer spent weeks optimizing does not fall apart because of a poorly routed metal layer.\nYou know the difference between a layout that passes DRC and one that actually works in silicon. When you see an LVS error, you do not panic, you trace it back to the source, whether it is a misaligned contact or a subtlety in the schematic that needs a conversation with the circuit team. At Synopsys, you will work on memory IP that ships in real products, and the layout decisions you make will directly affect performance, yield, and time to market.\nWhat You'll Be Doing\nDesign and implement full-custom layout for SRAM memory macros in advanced technology nodes, from bitcell to array to peripheral circuits\nOptimize layouts for area, performance, and power while maintaining design rule compliance and manufacturability\nRun and resolve DRC, LVS, ERC, Antenna, Density, and EM checks using Calibre, ICV, and other verification tools\nCollaborate directly with circuit designers to translate schematics into physical layouts that meet electrical and reliability specifications\nWork with process and foundry teams to interpret and apply technology files, design rules, and device models\nIterate on layout based on parasitic extraction results and post-layout simulation feedback\nThe Impact You Will Have\nYour layouts will directly determine the area efficiency, speed, and power consumption of SRAM macros used across Synopsys IP portfolios\nOptimized layout work you deliver will enable faster time to market for customers designing chips in leading-edge nodes\nClean DRC/LVS closure you achieve will reduce tapeout delays and prevent costly respins\nCollaboration with circuit teams will improve design quality and catch issues before they reach silicon\nYour expertise in advanced nodes will help Synopsys maintain leadership in memory IP competitiveness\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or Microelectronics\n1+ years of hands-on experience in SRAM or custom memory layout design\nStrong expertise in SRAM architecture, memory circuits, custom layout techniques, matching, symmetry, and device reliability\nProficiency with Cadence Virtuoso, Calibre, Custom Compiler, and ICV\nSolid understanding of DRC/LVS closure, RC extraction, and EM/IR considerations\nExperience with advanced technology nodes (7nm, 5nm, or below is a plus)\nWho You Are\nYou can look at a schematic and immediately start thinking about floorplan, device placement, and routing strategy\nWhen a DRC rule changes mid-project, you adapt quickly and figure out what needs to be reworked without losing momentum\nYou ask circuit designers the right questions about sensitivity, matching requirements, and performance targets before you start layout\nYou catch EM violations early because you have learned to think about current density while routing power, not after the fact\nYou are comfortable working across time zones with global teams when needed\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":4541,"description_truncated":false,"requirements":{"experience_years_min":1,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-10T11:17:58Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":18,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-11-11T05:49:22Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-layout-design-sr-engineer-19417","json_url":"https://alion.io/job/synopsys-layout-design-sr-engineer-19417.json","meta":{"generated_at":"2026-11-11T12:34:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22461,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-layout-design-sr-engineer-19417"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-layout-design-sr-engineer-19417"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-layout-design-sr-engineer-19417"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-layout-design-sr-engineer-19417\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-layout-design-sr-engineer-19417"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":4013358}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":4013358},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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