{"id":2328679,"url":"https://alion.io/job/synopsys-layout-design-staff-engineer-18883","title":"Layout Design, Staff Engineer - 18883","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-12T08:12:30Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-13T09:21:34Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the details of custom memory layout, and you know that the difference between a memory compiler that ships and one that stalls out is usually in how you handled density, matching, and DRC closure three weeks before tape-out. You think in layers, in device symmetry, in parasitic trade-offs. When a circuit designer hands you a schematic, you see not just what they drew but what they meant, and you know how to translate that intent into a layout that works across process corners and actually manufactures.\nYou do not wait for someone to tell you the DRC is broken. You catch it, you debug it, and you drive the fix. You have migrated designs across technology nodes and lived through the surprises that come with FinFET scaling. You can sit with a junior engineer and explain why their routing choice will create an antenna violation, and you can sit with a methodology team and push back when an automation script does not account for real layout constraints.\nAt Synopsys, you will work on memory IP that powers chips across the industry. The work is technical, the problems are real, and what you design will ship.\nWhat You'll Be Doing\nDesign and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff\nExecute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools\nDrive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules\nCollaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved\nDevelop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality\nReview layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges\nSupport customer-specific memory customization projects, working through optimization requests and delivering production-ready IP\nThe Impact You Will Have\nYour layouts will directly enable memory IP that ships in high-volume semiconductor products across automotive, mobile, AI, and data center applications\nYou will reduce design cycle time by improving layout automation and methodology, allowing the team to take on more projects with higher quality\nYour ability to close complex DRC and LVS issues independently will unblock project milestones and keep compiler development on schedule\nYou will raise the technical bar for the team by mentoring junior designers and establishing layout standards that scale across technology nodes\nYour collaboration with circuit and CAD teams will surface layout-driven insights that influence architecture and tool development decisions\nYou will help Synopsys deliver memory IP that meets the most demanding area, performance, power, and reliability requirements from leading semiconductor companies\nYour work on technology migrations will position the memory IP portfolio for next-generation nodes and maintain Synopsys leadership in the market\nWhat You'll Need\nBachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field\n8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development\nStrong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms\nDemonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques\nDeep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes\nExperience with parasitic extraction and physical verification flows, and the ability to interpret and act on results\nFamiliarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus\nWho You Are\nYou can debug a complex LVS mismatch by tracing through netlists, schematics, and layout views without needing someone to walk you through it\nYou know when to optimize for area and when to prioritize matching or performance, and you can explain the trade-off to a circuit designer in a way that moves the decision forward\nYou review a junior engineer's layout and give feedback that is specific, actionable, and grounded in what will actually cause problems downstream\nYou work across teams with circuit designers, methodology engineers, and CAD without losing sight of what you are trying to deliver or when it needs to be done\nYou stay current on process technology changes and layout challenges that come with new nodes, and you bring that knowledge into your daily work\nYou take ownership of your projects and deliver milestones with limited supervision, raising issues early when dependencies or risks emerge\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6017,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-12T08:12:30Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":12,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-layout-design-staff-engineer-18883","json_url":"https://alion.io/job/synopsys-layout-design-staff-engineer-18883.json","meta":{"generated_at":"2026-10-13T13:02:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20312,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-layout-design-staff-engineer-18883"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-layout-design-staff-engineer-18883"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-layout-design-staff-engineer-18883"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-layout-design-staff-engineer-18883\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-layout-design-staff-engineer-18883"}]}