{"id":519365,"url":"https://alion.io/job/synopsys-pcie-digital-design-sr-staff-engineer-18307","title":"PCIe Digital Design, Sr Staff Engineer-18307","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":73,"ghost_share":0.055,"stale_share":0,"repost_share":0.205,"time_to_fill_p50_days":15,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tokyo, Japan"],"countries":["JP"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":62000,"max_usd":130000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-07T22:53:51Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-30T16:38:03Z","board_verified":true,"closed_at":null,"days_open":52,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":51},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are a digital design engineer who takes pride in delivering RTL that is not only functionally correct, but also clean, synthesizable, and ready for real silicon. You enjoy working through the details-timing, CDC, lint, and design quality-because you know they matter when IP ships in customer products.\nYou work well in a collaborative, global environment. You communicate openly with design, verification, and implementation teammates, ask thoughtful questions when specs are unclear, and are willing to learn new tools and methodologies, including AI-driven design approaches. Whether you are deepening your expertise or guiding others through complex challenges, you bring ownership, curiosity, and a practical mindset to your work.\nWhat You'll Be Doing\nUnderstand industry standards and functional specifications, and contribute to architecture and micro-architecture definitions for complex protocol IP cores\nDesign and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog, balancing performance, area, power, synthesizability, and testability\nPerform basic verification and collaborate with verification teams on test planning, assertion development, functional debug, and coverage closure\nPerform RTL-level timing analysis during RTL development, and collaborate with implementation teams on STA, timing constraints, and synthesis as needed\nSupport CDC/RDC/Lint signoff readiness and collaborate on design-quality closure\nApply and explore AI-driven design tools and methodologies to improve design quality and automation\nThe Impact You Will Have\nYour RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide\nYou will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs\nYour collaboration will catch issues earlier, reducing costly respins and late-stage fixes\nThe automation you build will improve design productivity for your team and beyond\nYour attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk\nWhat You'll Need\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field\n4~15+ years of experience in digital design and/or RTL development\nHands-on experience designing and implementing synthesizable RTL in Verilog/SystemVerilog, with understanding of performance, area, power, and testability tradeoffs\nExperience with test planning, assertion development, basic verification, functional debug, and coverage closure\nExperience performing RTL-level timing analysis, with practical understanding of STA, timing constraints, and synthesis\nExperience with CDC/RDC/Lint signoff-ready design practices and design-quality closure\nScripting experience in Python, Tcl, Perl, or Shell\nWritten and oral communication skills in English and Japanese, with the ability to collaborate effectively across teams\n\n(Nice to Have)\nDirect experience with PCIe or CXL IP design and development\nExperience with low-power design and power intent development using UPF\nExposure to UVM or formal verification concepts\nExposure to functional safety concepts, ISO 26262, or FMEDA\nExperience mentoring engineers or serving as a technical lead on RTL/IP development projects\nPrior experience in a global product engineering environment\nWho You Are\nYou take ownership of your work and follow through on issues until they are properly resolved\nYou collaborate openly across teams and communicate clearly in both Japanese and English\nYou stay curious and adapt quickly to new tools, flows, and technical challenges\nYou balance attention to detail with practical judgment-you know when to dig deep and when to ask for help\nYou share knowledge with teammates and contribute to a supportive, learning-oriented team culture\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5002,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"Japanese","level":"All levels","optional":false},{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-07T22:53:51Z"},{"event":"close","at":"2026-09-14T10:55:12Z"},{"event":"reopen","at":"2026-09-14T13:55:24Z"}],"visa":[],"liveness":{"score":23,"band":"cold","label":"Long shot","p_open":1,"p_active":0.654,"p_room":0.35,"age_days":52,"expected_fill_days":15,"reasons":["conf:2","velocity","win:tail","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-pcie-digital-design-sr-staff-engineer-18307","json_url":"https://alion.io/job/synopsys-pcie-digital-design-sr-staff-engineer-18307.json","meta":{"generated_at":"2026-10-30T21:02:26Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11359,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-pcie-digital-design-sr-staff-engineer-18307"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-pcie-digital-design-sr-staff-engineer-18307"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-pcie-digital-design-sr-staff-engineer-18307"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-pcie-digital-design-sr-staff-engineer-18307\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-pcie-digital-design-sr-staff-engineer-18307"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":519365}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":519365},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}