{"id":519325,"url":"https://alion.io/job/synopsys-rd-engineering-director","title":"R&D Engineering, Director","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":90,"ghost_share":0.033,"stale_share":0,"repost_share":0.144,"time_to_fill_p50_days":10,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-07T22:53:51Z","employer_posted_date":"2026-09-14","last_verified_at":"2026-10-02T00:31:24Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":24},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent two decades building embedded memory IP that actually ships in products, not just passes tape-out reviews, and you know the difference between a circuit that works in simulation and one that survives process variation at 3nm. Leading teams is not about org charts for you, it is about knowing when to step into a schematic review because the bit cell leakage numbers do not add up, and when to step back because your engineer has the answer but needs space to find it.\nYou think in full flows. Architecture decisions ripple into layout constraints, layout choices show up in characterization data, and characterization data feeds back into compiler automation. You have debugged enough memory compiler issues to know that the problem is rarely where it first appears, and you ask the kind of questions that get to root cause without wasting three days.\nManaging multiple projects across FinFET nodes does not rattle you. You prioritize without drama, communicate blockers before they become crises, and keep your team focused on what actually moves the schedule. When a customer escalates a timing model issue, you do not deflect, you own it, pull in the right people, and drive it closed.\nAt Synopsys, you will lead a team that builds the memory IP behind the semiconductors powering AI, automotive, and mobile products worldwide.\nWhat You'll Be Doing\nLead a team of memory design engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations for advanced process nodes including FinFET\nOwn the full memory design flow from bit cell analysis and architecture through schematic entry, simulation, layout planning, characterization, verification, and model generation\nDrive low-power, area-efficient embedded memory circuit design and supervise layout activities, interfacing directly with CAD teams on verification and compiler automation\nManage project timelines, prioritize tasks across multiple concurrent projects, and resolve technical and scheduling issues proactively to ensure on-time delivery\nBuild and maintain relationships with cross-functional teams including characterization, verification, and customer-facing engineering to align on deliverables and resolve escalations\nApply and expand expertise in memory compiler development, transistor-level circuit design, and variation-aware design techniques for deep submicron technologies\nMentor engineers, facilitate technical problem-solving, and foster collaboration across multi-site teams in Hyderabad and globally\nThe Impact You Will Have\nDeliver embedded memory IP that powers leading-edge semiconductor products across AI, automotive, mobile, and high-performance computing markets\nEnable Synopsys customers to meet aggressive area, power, and performance targets by providing robust, scalable memory solutions that work in silicon\nReduce time-to-market for memory compiler releases by streamlining design flows, improving automation, and catching issues earlier in the development cycle\nStrengthen Synopsys reputation as a trusted memory IP partner by resolving customer escalations quickly and delivering high-quality timing and power models\nBuild a high-performing team culture where engineers grow technically, take ownership, and consistently deliver complex projects on schedule\nDrive process improvements that increase team productivity, reduce characterization cycles, and improve compiler quality metrics\nShape the technical direction of embedded memory IP development at Synopsys by contributing expertise in advanced node challenges and circuit innovation\nWhat You'll Need\nBE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering from a recognized university\n20+ years of hands-on experience in embedded memory design including SRAM, Register File, TCAM, and ROM architecture and circuit implementation\nDeep expertise across the full memory design flow: architecture, schematic design, layout planning, characterization, timing analysis, and model generation\nProven experience leading and managing engineering teams, delivering complex projects on schedule, and resolving technical and project issues across multiple priorities\nStrong proficiency in transistor-level circuit design for deep submicron and FinFET technologies, including variation-aware design techniques\nMastery of Perl and Python for design automation and scripting\nExperience with memory compiler development and automation is a strong plus\nWho You Are\nYou can walk into a schematic review, spot a leakage path or timing violation in minutes, and explain the fix in a way that helps the engineer learn, not just comply\nWhen a project is slipping, you do not wait for the weekly status meeting, you pull the team together, identify the real blocker, and adjust the plan that day\nYou know how to say no to a customer request that will derail the schedule without burning the relationship, and you can explain the tradeoff in terms they actually care about\nDebugging a characterization mismatch across process corners does not frustrate you, it engages you, because you know the answer is in the data and you will find it\nYou build trust by doing what you say you will do, owning mistakes when they happen, and giving your team credit when things go right\nYou are comfortable working across time zones and geographies, and you adapt your communication style to make sure nothing gets lost in translation\nThe Team You'll Be Part Of\nYou will lead a team within the Embedded Memory and Logic group at Synopsys, part of the Solutions Group. This team is responsible for developing standard and custom embedded SRAMs, ROMs, and TCAMs, delivering both functional and physical memory views through advanced memory compilers. The team covers the full spectrum of memory IP development, from bit cell analysis and architecture design to characterization, verification, and model generation. Your team will work closely with CAD, verification, and customer-facing engineering teams across Synopsys global sites to deliver memory IP that enables the design of complex integrated circuits for leading-edge semiconductor products.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":7175,"description_truncated":false,"requirements":{"experience_years_min":20,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-07T22:53:51Z"},{"event":"close","at":"2026-09-11T01:53:52Z"},{"event":"reopen","at":"2026-09-14T07:54:07Z"}],"liveness":{"score":26,"band":"fade","label":"Fading","p_open":1,"p_active":0.73,"p_room":0.35,"age_days":24,"expected_fill_days":10,"reasons":["conf:5","velocity","win:tail","comp:brand"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-director","json_url":"https://alion.io/job/synopsys-rd-engineering-director.json","meta":{"generated_at":"2026-10-03T03:50:08Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3821,"day_limit":5000,"remaining_today":1179,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}