{"id":3546858,"url":"https://alion.io/job/synopsys-rd-engineering-scientist","title":"R&D Engineering, Scientist","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":65,"ghost_share":0.046,"stale_share":0,"repost_share":0.2,"time_to_fill_p50_days":17,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Science & Research","role_family":"Science & Research","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":72000,"max_usd":198000,"period":"year","method":"role_country_seniority_unknown","sample_n":3270},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-10-30T21:06:36Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-05T18:32:51Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"Job Description and Requirements\nWe Are\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips. Join us to transform the future through continuous technological innovation.\nYou Are\nYou are an experienced PHY and SerDes architect with deep knowledge of high-speed serial links. You translate complex protocol, channel, and system requirements into implementable architectures while balancing power, performance, area, latency, and reliability. You communicate effectively across analog, digital, signal-integrity, package, program, and customer-facing teams.\nWhat You’ll Be Doing\nOwn the PHY architecture, including protocols, data rates, BER, and PPA targets.\nDefine data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.\nLead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.\nAllocate power, area, performance, and latency across analog, digital, and package components.\nDevelop block specifications that engineering teams can implement and verify.\nClose the end-to-end link budget across the transmitter, package, channel, and receiver.\nDefine architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.\nAlign standards, signal and power integrity, package, and program teams on guaranteed IP performance.\nThe Impact You Will Have\nDefine advanced 112 Gb/s and 224 Gb/s PAM4 PHY architectures.\nImprove first-silicon success through rigorous link budgeting, modeling, and observability.\nReduce integration risk by establishing clear cross-functional specifications and sign-off criteria.\nEnable differentiated, high-performance interface IP for advanced silicon applications.\nWhat You’ll Need\nStrong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.\nExpertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.\nDeep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.\nExperience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.\nSilicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.\nDemonstrated ability to write clear technical specifications and explain architecture decisions to technical, program, and customer audiences.\nWho You Are\nA systems thinker who connects circuit-level decisions to end-to-end link performance.\nA collaborative technical leader who works effectively across disciplines and geographies.\nA clear communicator who translates complex tradeoffs into actionable decisions.\nA pragmatic problem solver focused on quality, performance, and silicon success.\nThe Team You’ll Be a Part Of\nYou will join a multidisciplinary team developing advanced high-speed PHY IP. You will collaborate with analog, digital, verification, signal-integrity, power-integrity, package, and silicon-validation teams to deliver measurable and differentiated system performance.\nRewards and Benefits\nWe offer comprehensive health, wellness, and financial benefits. Our total rewards include monetary and non-monetary offerings. Your recruiter will provide additional details during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.","description_format":"text","description_chars":4317,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-30T21:06:36Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 178 · green card filings: 177","filings_12m":178,"filings_prev_12m":208,"green_card_filings_12m":177,"median_offered_wage_usd":157472,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":84,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.845,"p_room":1,"age_days":5,"expected_fill_days":17,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-11-05T05:54:30Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-scientist","json_url":"https://alion.io/job/synopsys-rd-engineering-scientist.json","meta":{"generated_at":"2026-11-05T21:16:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":940,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-rd-engineering-scientist"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-rd-engineering-scientist"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-rd-engineering-scientist"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-rd-engineering-scientist\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-rd-engineering-scientist"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3546858}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3546858},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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