{"id":3951886,"url":"https://alion.io/job/synopsys-rd-engineering-sr-engineer-17877","title":"R&D Engineering, Sr Engineer - 17877","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":64,"ghost_share":0.047,"stale_share":0,"repost_share":0.188,"time_to_fill_p50_days":18,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Siemens Calibre","optional":false},{"name":"Synopsys HSPICE","optional":false}],"status":"live","first_seen_at":"2026-11-09T04:16:26Z","employer_posted_date":"2026-11-09","last_verified_at":"2026-11-09T04:16:26Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAlternate Job Titles\nSenior/Staff Memory Circuit Design Engineer\nSenior/Staff Circuit Design Engineer \nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the physics of memory circuits, and you understand that the difference between a TCAM that works at spec and one that ships is often a single transistor decision made during bitcell layout. You think in tradeoffs: speed versus power, density versus reliability, and you know which lever to pull when a customer asks for all three at once.\nYou are the kind of engineer who can look at a schematic, spot the weak path before simulation confirms it, and already be sketching the fix. Layout is not something you hand off and forget, you work closely with layout engineers, walking through floor plans, parasitic concerns, and design rule challenges because you know that circuit performance lives or dies in the back end.\nAmbiguity does not stall you. When a new process node drops and the models are still rough, you start designing anyway, asking the right questions, building margin into your assumptions, and iterating as data firms up. You have debugged silicon that came back wrong, traced failures back through test vectors and SPICE decks, and walked out with a root cause and a plan.\nAt Synopsys, you will work on memory IP that powers everything from automotive SoCs to AI accelerators. The problems are hard, the nodes are advanced, and what you design will ship in products that matter.\nWhat You'll Be Doing\nDesign and develop CMOS special memory circuits including TCAM, BCAM, and multi-port SRAM for advanced process nodes\nOwn architecture definition and circuit implementation for ultra-high speed, ultra-low power, or high-density memory portfolios\nDrive schematic entry, circuit simulation, layout planning, and design verification from bitcell to full array\nCollaborate with CAD and frontend engineers to integrate designs into memory compiler flows and generate EDA models\nDevelop and verify bitcells, supervise physical layout design, and debug parasitic extraction results to meet performance targets\nSupport silicon bring-up and failure analysis, translating test data into design improvements for future releases\nThe Impact You Will Have\nYour memory designs will enable faster, lower-power chips across automotive, mobile, AI, and high-performance computing markets\nThe bitcells and architectures you develop will define performance benchmarks for Synopsys Foundation IP across multiple process nodes\nYour debugging and failure analysis will improve yield and robustness, reducing costly respins and accelerating customer adoption\nCollaboration with compiler teams will streamline design automation, reducing turnaround time for custom memory configurations\nMentorship you provide will build circuit design capability within the team, raising the technical bar for future releases\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related technical field\n3+ years of hands-on experience designing embedded CMOS memory circuits at 28nm or more advanced technology nodes\nProven experience with embedded memory design flow: architecture, circuit design, layout implementation, compiler integration, and timing model generation\nStrong proficiency in bitcell design, circuit simulation tools like HSPICE or Spectre, and layout parasitic extraction\nDeep understanding of SRAM, TCAM, BCAM, or multi-port memory architectures, with experience in failure analysis and memory test methodology\nExperience with layout verification tools such as Calibre or ICV, and ability to debug DRC, LVS, and ERC issues; experience with TCAM or multi-port SRAM is a strong plus\nWho You Are\nYou can explain a complex circuit tradeoff to a product manager in two sentences without losing the technical nuance\nWhen a simulation result does not match your intuition, you dig until you understand why, whether it is a model issue or a real design flaw\nYou are comfortable leading design reviews where you defend your architecture choices and incorporate feedback without losing momentum\nDebugging energizes you; you treat a silicon failure as a puzzle to solve, not a setback\nYou balance detail orientation with pragmatism, knowing when to push for another optimization round and when to lock the design\nThe Team You'll Be Part Of\nYou will join the Foundation IP team in Ho Chi Minh City, a group focused on developing memory compilers and special memory solutions for advanced process nodes. The team works closely with CAD, frontend, and characterization engineers to deliver high-performance, low-power memory IP that ships in customer designs worldwide.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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