{"id":1311294,"url":"https://alion.io/job/synopsys-rd-engineering-sr-engineer-18866","title":"R&D Engineering, Sr Engineer - 18866","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":96,"ghost_share":0.031,"stale_share":0,"repost_share":0.156,"time_to_fill_p50_days":7,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":15000,"max_usd":33000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":3947},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"JavaScript","optional":false},{"name":"Perl","optional":false},{"name":"Synopsys HSPICE","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:28:35Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-10-02T00:31:24Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Job Description and Requirements\nAlternate Job Titles\nEmbedded Memory Sr Engineer\nCMOS Memory Circuit Design Sr Engineer\nStaff Memory IP Design Engineer\nSRAM/ROM Compiler Sr Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years deep in the physics and trade-offs of embedded memory design, and you understand that a well-designed SRAM bitcell is not just smaller or faster, it is the difference between a chip that ships and one that does not. You know how leakage, stability, and performance interact at the transistor level, and you have debugged enough layout-versus-schematic mismatches to spot a problem before it becomes a tape-out delay.\nYou are comfortable moving between circuit simulation in SPICE, layout review with your physical design partners, and scripting in Perl or C-Shell to automate the repetitive parts so you can focus on the hard decisions. When a reliability issue surfaces late in a project, you do not panic. You pull the data, run the corners, talk to the foundry if needed, and find the root cause.\nMentorship matters to you. You have learned that the best way to scale your impact is to help the engineer next to you get better, whether that means walking through a Monte Carlo setup or explaining why a particular design choice will not hold up under process variation. At Synopsys, you will work on memory IP that goes into chips used across automotive, mobile, AI, and data center applications.\nWhat You'll Be Doing\nDesign and optimize embedded memory circuits including SRAM, ROM, and Register File blocks for advanced process nodes\nLead bitcell development from concept through characterization, including transistor-level simulation, corner analysis, and reliability validation\nSupervise and collaborate with layout engineers to ensure design intent is maintained through physical implementation\nWork with CAD and compiler teams to integrate memory designs into automated generation flows and verification environments\nDrive yield and performance improvements by analyzing silicon data, identifying failure modes, and iterating on design or test methodologies\nMentor junior engineers on circuit design techniques, simulation best practices, and design-for-manufacturability principles\nThe Impact You Will Have\nDeliver memory IP that powers semiconductor products across automotive, mobile, AI, and high-performance computing markets\nImprove memory compiler quality and turnaround time by tightening integration between circuit design and automation infrastructure\nReduce time-to-market for new process nodes by building reusable, well-characterized bitcell libraries and design methodologies\nStrengthen the technical capability of the team by sharing knowledge, reviewing designs, and establishing best practices that scale\nSolve yield and reliability issues that directly affect customer tape-outs and production ramps\nEnable cross-functional teams including verification, product engineering, and applications to resolve complex technical challenges faster\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical discipline\n2+ years of hands-on experience in embedded CMOS memory design, with a focus on SRAM, ROM, or Register File development\nDeep expertise in SRAM bitcell design, including read/write stability analysis, leakage optimization, and statistical variation modeling\nProficiency with circuit simulation tools such as HSPICE or Spectre, and layout tools for design review and verification\nStrong scripting skills in C-Shell and Perl for automation and data analysis, experience with C++ or JavaScript is a plus\nFluency in English and Vietnamese for technical communication and collaboration across global teams\nWho You Are\nYou approach complex problems methodically, breaking them into testable hypotheses and iterating based on data rather than intuition alone\nYou communicate technical trade-offs clearly to engineers, managers, and occasionally customers, without losing the nuance that matters for decision-making\nYou take ownership of your designs from initial concept through silicon bring-up, and you follow through when issues arise post-tapeout\nYou are organized enough to manage multiple design tasks, reviews, and mentorship responsibilities without dropping threads or missing deadlines\nYou collaborate naturally with layout engineers, verification teams, and CAD developers, understanding that great memory IP is a team effort\nThe Team You'll Be Part Of\nYou will join the embedded memory IP team in Ho Chi Minh City, a group focused on developing next-generation SRAM, ROM, and Register File compilers for advanced process nodes. The team works closely with Synopsys's global memory design community, foundry partners, and product engineering teams to deliver memory solutions that meet the performance, power, and area requirements of leading semiconductor companies.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5896,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"Vietnamese","level":"Advanced (C1)","optional":false},{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:28:35Z"}],"liveness":{"score":71,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.787,"p_room":0.9,"age_days":4,"expected_fill_days":7,"reasons":["conf:20","velocity","win:mid","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-sr-engineer-18866","json_url":"https://alion.io/job/synopsys-rd-engineering-sr-engineer-18866.json","meta":{"generated_at":"2026-10-02T01:38:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2051,"day_limit":5000,"remaining_today":2949,"minute_limit":60,"resets_at":"2026-10-03T00:00:00Z"}}}