{"id":1311219,"url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-16978","title":"R&D Engineering, Staff Engineer - 16978","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":99,"ghost_share":0.03,"stale_share":0,"repost_share":0.162,"time_to_fill_p50_days":7,"computed_at":"2026-09-30T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":375},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Copilot","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-30T09:23:48Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and experienced software engineer who thrives in a collaborative, fast-paced environment. You bring a deep understanding of C/C++, object-oriented programming, and complex data structures, coupled with a robust foundation in RTL design methodologies and synthesis concepts. Your hands-on experience with large-scale software systems enables you to deliver high-quality, high-performance solutions that make a tangible impact on end users. You enjoy tackling challenging problems, applying analytical thinking to drive innovation, and leveraging AI productivity tools to enhance your workflow. With a strong desire to learn and stay ahead of emerging technologies, you are eager to explore new domains and contribute to groundbreaking advancements in EDA. You are comfortable working independently, guiding junior peers, and engaging with cross-functional teams to achieve common goals. Above all, you value inclusivity, clear communication, and continuous improvement, and you are motivated by opportunities to shape the next generation of chip design tools.\nWhat You’ll Be Doing:\nDesigning and developing advanced RTL analysis, restructuring, and optimization technologies within RTL Architect. \nImplementing efficient algorithms and data structures to enhance quality of results (QoR) and performance of architectural exploration tools. \nCollaborating with product teams to integrate new features and support customer-driven requirements. \nUtilizing AI productivity tools such as cursor and GitHub Copilot to accelerate development cycles and improve code quality. \nConducting rigorous testing and validation of software modules to ensure reliability and scalability. \nMentoring and guiding junior engineers, fostering a culture of innovation and technical excellence.\nThe Impact You Will Have:\nStrengthen Synopsys’ leadership in RTL-driven architectural exploration through delivery of advanced restructuring and optimization technologies. \nDirectly improve product quality and customer productivity, enabling faster time-to-market for leading semiconductor companies. \nDrive wider adoption of RTL Architect by enhancing user experience and delivering measurable value. \nReduce downstream implementation risk for customers by enabling early architectural exploration and QoR convergence. \nSupport long-term business growth by contributing to strategic technology initiatives and product innovation. \nFoster a collaborative and inclusive engineering environment that empowers team members to achieve their best.\nWhat You’ll Need:\nStrong proficiency in C/C++ and object-oriented design principles. \n4 to 10 years of experience in EDA Software development\nSolid understanding of data structures, graphs, and algorithms. \nExpertise in RTL design methodologies (Verilog, SystemVerilog, VHDL). \nDeep knowledge of synthesis and optimization concepts in EDA. \nExperience working on large, complex software systems with a focus on quality and performance. \nHands-on familiarity with AI productivity tools such as cursor and GitHub Copilot.\nWho You Are:\nAnalytical thinker and creative problem solver. \nSelf-driven with the ability to work independently and take initiative. \nCollaborative team player who enjoys mentoring others. \nExcellent communicator, able to convey technical concepts clearly. \nAdaptable and eager to learn new technologies and methodologies. \nCommitted to fostering an inclusive and innovative work environment.\nThe Team You’ll Be A Part Of:\nYou will join a dynamic R&D team focused on advancing RTL analysis, restructuring, and optimization technologies within RTL Architect. This team enables early architectural exploration and QoR convergence, helping customers make informed design decisions and reduce downstream implementation risk. Our collaborative culture emphasizes technical excellence, continuous learning, and impactful innovation, empowering each member to drive meaningful change in the EDA industry.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":4987,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"liveness":{"score":66,"band":"ok","label":"Likely open","p_open":0.9,"p_active":0.815,"p_room":0.9,"age_days":3,"expected_fill_days":7,"reasons":["conf:81","velocity","win:mid","comp:brand"],"computed_at":"2026-09-30T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-16978","json_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-16978.json","meta":{"generated_at":"2026-10-01T03:05:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2572,"day_limit":5000,"remaining_today":2428,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}