{"id":2328673,"url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-17912","title":"R&D Engineering, Staff Engineer - 17912","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":76,"ghost_share":0.053,"stale_share":0,"repost_share":0.211,"time_to_fill_p50_days":15,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":51000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-12T08:12:30Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-29T09:22:26Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building Verification IP that engineers actually trust, not just IP that passes a checklist. You know that a VIP is only as good as the edge cases it catches and the clarity it brings when something breaks at 2 a.m. in a customer lab. Debugging a protocol violation three layers deep does not frustrate you, it pulls you in because finding the root cause matters more than closing a ticket.\nYou think in coverage metrics and corner cases. When you read a protocol spec, you are already mapping out the sequences that will stress the implementation in ways the design team has not considered yet. You have worked with NVMe, PCIe, USB, Ethernet, or similar protocols long enough to know where the gaps usually hide and what good verification architecture looks like when it scales across products and customers.\nWorking directly with customers during deployment does not feel like a distraction, it feels like the part where you learn what actually matters. You bring tasks to closure because leaving something half done keeps you up at night. At Synopsys, you will work with protocol experts, Design IP teams, and some of the best verification tooling in the industry, and what you build will ship into semiconductor development workflows worldwide.\nWhat You'll Be Doing\nDesign, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including AMBA, PCIe, USB, Ethernet, UEC, UAL, and MIPI\nBuild comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies\nCode sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions\nDebug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments\nEnhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand\nSupport customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up\nCollaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs\nThe Impact You Will Have\nYour VIP will enable faster, more reliable verification for semiconductor companies building next-generation SoCs and AI-powered products\nCoverage-driven verification strategies you implement will catch critical protocol violations before they reach silicon, saving months of debug time downstream\nEnhancements you make to existing VIP products will improve performance and expand protocol support across the Synopsys IP portfolio\nCustomer deployments you support will directly influence how engineers at leading semiconductor companies adopt and trust Synopsys VIP\nVerification plans you create will set the standard for how protocol compliance is validated across complex, multi-protocol designs\nCollaboration with Design IP teams will tighten the feedback loop between design and verification, improving quality across both disciplines\nYour work will contribute to a VIP product line used globally in semiconductor development, affecting how chips are verified at scale\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience\n5+ years of hands-on experience developing Verification IP\nStrong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments\nSpecializing in NVMe protocols (mandatory) and PCIe (desirable) or Deep working knowledge of at least two industry-standard protocols USB, Ethernet or MIPI\nThe ideal candidate should have hands-on experience with BFM, IP, or VIP development and integration.\nThe role requires a solid understanding of verification methodologies and protocol compliance. Strong problem-solving skills and the ability to work independently or as part of a team are important.\nDemonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis\nExperience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries\nExperience working directly with customers or field teams during product deployment is a strong plus\nExcellent communication skills and a proactive approach to technical challenges are highly valued.\nWho You Are\nYou can read a protocol specification and translate it into a verification plan that covers not just the happy path but the corner cases that break real designs\nDebugging a failing sequence across thousands of lines of log output does not drain you, it engages you because you know the answer is in there somewhere\nYou bring strong opinions about what good VIP architecture looks like, and you are willing to push back when a shortcut will create technical debt six months from now\nWorking with customers during integration feels like a natural extension of your work, not a context switch, because you want to see your VIP succeed in the field\nYou are organized enough to manage multiple VIP enhancements, customer issues, and verification plans in parallel without losing track of quality or deadlines\nWhen a task is 90% done, you are the person who finishes the last 10%, writes the documentation, and makes sure it actually works before calling it complete\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6642,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-12T08:12:30Z"}],"visa":[],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.826,"p_room":0.55,"age_days":16,"expected_fill_days":15,"reasons":["conf:0","velocity","win:tail","comp:brand"],"computed_at":"2026-10-29T05:49:05Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-17912","json_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-17912.json","meta":{"generated_at":"2026-10-29T10:50:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16430,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-rd-engineering-staff-engineer-17912"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-rd-engineering-staff-engineer-17912"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-rd-engineering-staff-engineer-17912"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-rd-engineering-staff-engineer-17912\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-rd-engineering-staff-engineer-17912"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2328673}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2328673},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}