{"id":1311223,"url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-18271","title":"R&D Engineering, Staff Engineer- 18271","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":99,"ghost_share":0.03,"stale_share":0,"repost_share":0.162,"time_to_fill_p50_days":7,"computed_at":"2026-09-28T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":52000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":944},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"JavaScript","optional":false},{"name":"Perl","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys HSPICE","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T19:50:00Z","board_verified":false,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Job Description and Requirements\nStaff Memory Design EngineerWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in the analog and mixed-signal trenches, designing memory circuits that have to work across voltage corners, temperature extremes, and process variations without a second chance. You know that an SRAM bitcell is not just six transistors on a page, it is a tradeoff between read stability, write margin, leakage, and area, and you have made those calls enough times to know which knob to turn when a design is not closing.\nYou think in terms of transistor-level behavior, not just simulation results. When a memory fails at a corner, you do not just re-run SPICE, you go back to the schematic, check your layout parasitics, and figure out what actually broke. You have worked closely with layout teams, and you understand that a good floorplan saves you three weeks of iteration later.\nYou are comfortable owning a memory block from architecture through tapeout. You can sit with a compiler team and explain why your bitcell needs a specific routing constraint, then turn around and review a layout with a physical design engineer without losing context. At Synopsys, you will design embedded memories that ship in our IP portfolio and power chips across the industry.\nWhat You'll Be Doing\nDesign and develop embedded CMOS memories including single-port SRAM, dual-port SRAM, register files, and ROM for Synopsys IP products\nOwn circuit architecture and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations\nPerform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification\nDevelop and verify bitcells, define layout rules, and drive layout design and parasitic extraction closure with the physical design team\nInterface with CAD teams to integrate memory designs into compiler automation flows and generate EDA models for customer use\nCollaborate with frontend engineers to define and validate full verification flows including timing, power, and functional models\nMentor junior engineers and lead technical aspects of memory design projects from concept to delivery\nThe Impact You Will Have\nYour memory designs will ship as part of Synopsys IP offerings used by semiconductor companies worldwide in high-volume production chips\nThe bitcells and architectures you develop will define performance, power, and area benchmarks for next-generation embedded memory IP\nYour layout planning and verification rigor will reduce tapeout risk and speed time to market for memory compiler releases\nThe automation flows you help define will enable faster, more reliable memory generation for customers across process nodes\nYour technical mentorship will build design capability within the team and raise the quality bar for future memory products\nThe tradeoffs you make between speed, power, and density will directly influence customer adoption and competitiveness in the IP market\nYour collaboration with CAD and frontend teams will improve tooling, models, and verification coverage across the memory IP portfolio\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Electronics, or a related technical field\nDeep hands-on experience with CMOS memory circuit design including SRAM, register files, or ROM\nProficiency with circuit simulation tools such as HSPICE, Spectre, or similar SPICE-based simulators\nStrong understanding of memory layout design, parasitic extraction, and layout verification tools like Calibre or Assura\nScripting capability in C-Shell, Perl, or similar languages; experience with C++ or JavaScript is a plus\nDemonstrated ability to lead technical projects and mentor junior engineers through complex design challenges\nExperience working with memory compiler flows, EDA model generation, or design automation is a strong plus\nWho You Are\nYou can look at a bitcell schematic and immediately spot a read stability issue or a leakage path without running a full simulation\nYou know how to work with layout designers, not just hand off a schematic and hope for the best, you review floorplans, flag routing issues, and iterate together\nYou are comfortable making technical tradeoffs in ambiguity, choosing between a faster access time and lower leakage when the spec does not give you both\nYou can explain a circuit-level design decision to a compiler engineer or a product manager in terms they understand without oversimplifying the engineering\nYou stay organized across multiple design blocks, verification runs, and layout reviews without losing track of what is blocking tapeout\nYou take ownership, if a memory fails characterization, you do not wait for someone else to debug it, you dig in and figure out what went wrong\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":5906,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.859,"p_room":1,"age_days":1,"expected_fill_days":7,"reasons":["conf:33","velocity","win:early","comp:brand"],"computed_at":"2026-09-28T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-18271","json_url":"https://alion.io/job/synopsys-rd-engineering-staff-engineer-18271.json","meta":{"generated_at":"2026-09-29T03:09:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2852,"day_limit":5000,"remaining_today":2148,"minute_limit":60,"resets_at":"2026-09-30T00:00:00Z"}}}