R&D Engineering, Staff Engineer-19130

Job Description and Requirements

Alternate Job Titles

• Library Validation Engineer
• Library Development and Release Engineer
• Power Library Modeling Engineer
• Semiconductor Library Engineer
• IP Library Validation Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building and validating semiconductor libraries that have to work in production, not just pass a test suite. You know that a library view delivered without proper power modeling or incomplete validation creates a cascade of problems for design teams three months later, and you are the kind of engineer who catches those gaps before they ship. You think in terms of flows, not just files. When you see a library deliverable, you are already mapping the characterization chain, the build dependencies, the APL model generation steps, and the release checkpoints that need to happen for it to land correctly.

Debugging does not intimidate you. Whether it is a SPIPROF model mismatch, a CDEV extraction issue, or a release flow that broke overnight, you dig in, trace the root cause, and fix it with clarity. You automate the repetitive parts because you have better things to do than run the same validation script manually for the tenth time. Python and Shell are tools you reach for without thinking, and you have built enough automation to know what makes a script maintainable versus what makes it a liability six months later.

At Synopsys, you will work on libraries and power models that enable real chips to tape out. The work is technical, the standards are high, and what you validate matters.

What You'll Be Doing

• Create and validate library views across multiple formats and technology nodes to support diverse design and signoff requirements
• Develop, validate, and package library deliverables for internal teams and external customer releases, ensuring completeness and correctness
• Generate and validate Apache Power Library models including SPIPROF, Current, CDEV, and PWCDEV for power integrity and signoff flows
• Execute comprehensive quality checks across library builds, APL models, and release packages to catch issues before they reach downstream users
• Debug and resolve complex issues in characterization flows, APL model generation, build validation, and release processes
• Build and maintain Python and Shell automation to improve validation coverage, reduce manual effort, and increase release velocity
• Collaborate with characterization, design, CAD, QA, and release teams to align on requirements, troubleshoot blockers, and deliver on schedule

The Impact You Will Have

• Enable design teams and customers to meet tape-out schedules by delivering high-quality, validated library deliverables on time
• Reduce downstream design issues by catching library and APL model inconsistencies early through rigorous validation
• Accelerate release cycles by building automation that replaces manual validation steps and improves flow reliability
• Improve power signoff accuracy by delivering validated SPIPROF, CDEV, and PWCDEV models that reflect real silicon behavior
• Drive quality improvements across the library development pipeline by identifying gaps in validation coverage and closing them
• Solve customer-reported library and APL issues quickly, reducing support escalations and maintaining customer trust
• Contribute to continuous improvement efforts that make validation flows faster, more robust, and easier to maintain

What You'll Need

• Bachelor's or Master's in Electronics Engineering, Computer Science, or equivalent practical experience
• 5+ years of hands-on experience in library development, validation, or characterization for semiconductor IP or EDA flows
• Strong proficiency in Python and Shell scripting for automation, validation, and workflow orchestration
• Deep understanding of library views, formats, and their role in digital and custom design flows
• Experience with Apache Power Library models such as SPIPROF, Current, CDEV, or PWCDEV is a strong plus
• Solid debugging skills across complex multi-step flows involving characterization, model generation, and release processes
• Ability to work across teams and communicate technical issues clearly to design, CAD, QA, and release stakeholders

Who You Are

• You can trace a library issue from a customer report back through the build flow, characterization run, and source data without getting lost
• You write automation that other engineers can actually use, not just scripts that work on your machine
• You know when to escalate and when to dig deeper, and you do not let blockers sit unresolved while you wait for someone else to fix them
• You can explain a complex APL model discrepancy to a design engineer in two minutes without losing the technical detail that matters
• You care about the quality of what ships, not just whether it passed the checklist
• You are comfortable working in a global team across time zones, asynchronously when needed and in real time when it helps

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.