{"id":2092627,"url":"https://alion.io/job/synopsys-soc-engineering-architect-19169","title":"SOC Engineering, Architect-19169","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":89,"ghost_share":0.034,"stale_share":0,"repost_share":0.169,"time_to_fill_p50_days":11,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":169000,"max_usd":306000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":469},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-08T15:20:40Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-12T19:36:21Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent the better part of your career translating product ambition into silicon reality. You know that the hardest part of any SoC is not the individual IP blocks, it is making them work together as a coherent system that actually ships. You think in subsystems, not just components. You have sat in enough bring-up sessions to know that the decisions you make today about interconnect topology, power domains, or protocol alignment will either save or cost your team six months down the line.\nYou are comfortable walking into a room with conflicting requirements from software, verification, and implementation teams and walking out with an architecture that makes sense for all of them. You do not need perfect specs to start. You ask the right questions, model the critical paths, and make the call. You have a point of view on what makes a subsystem robust, and you are not afraid to push back when a proposal does not hold up under real-world constraints. At Synopsys, you will work on IP subsystems that power everything from automotive AI to 5G infrastructure, and the architecture decisions you make will matter.\nWhat You'll Be Doing\nDefine subsystem architectures for memory controllers, interconnect clusters, compute blocks, power management units, or communication subsystems, translating product requirements into detailed specs that balance performance, power, area, security, and functionality\nIntegrate multiple IP blocks into cohesive subsystems, ensuring proper interoperability, dataflow alignment, and interface compatibility with SoC-level interconnects and firmware requirements\nLead architecture exploration activities including IP selection, subsystem modeling, and validation of candidate architectures using simulation and analysis tools\nCoordinate with SoC architects, verification teams, software engineers, and physical design groups to ensure subsystem feasibility, correctness, and alignment with platform constraints\nDefine verification requirements for subsystem functionality, performance corner cases, power states, and protocol compatibility, working with DV teams to ensure comprehensive validation coverage\nProduce architecture documents, subsystem specifications, engineering guidelines, and implementation requirements that clearly communicate architectural intent to technical and non-technical stakeholders\nParticipate in silicon bring-up, debug sessions, and subsystem-level performance characterization to validate architectural decisions in real hardware\nWhat You'll Need\nBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 15+ years of overall semiconductor experience\n10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles with proven track record of delivering complex subsystems to production\nDeep expertise in Verilog and SystemVerilog for RTL design and simulation, with hands-on experience using industry-standard simulation tools\nStrong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol-level debugging and performance analysis\nExperience with synthesis, lint, CDC, low power design flows, and verification closure using SystemVerilog UVM, BFM development, or test environment creation\nDemonstrated ability to coordinate cross-disciplinary teams including hardware, firmware, software, verification, and physical design groups to drive complex projects to completion\nExcellent technical writing and communication skills with a track record of producing clear architecture documents and specifications that drive alignment across diverse engineering teams\nThe Impact You Will Have\nEnable faster time to market for customers building AI-powered products, automotive systems, 5G infrastructure, and IoT devices by delivering differentiated subsystem solutions that reduce integration risk\nShape the architectural direction of Synopsys Digital IP Subsystems, influencing how millions of chips get designed and manufactured across the semiconductor industry\nReduce design respins and costly late-stage fixes by catching architectural issues early through rigorous subsystem-level modeling and validation\nAccelerate product development cycles for internal teams by providing clear, implementable subsystem architectures that align hardware, software, and verification efforts from day one\nMentor engineers across disciplines, raising the bar for subsystem design methodologies and best practices that will scale across future product generations\nDrive architectural innovation in critical areas like power efficiency, performance optimization, and protocol interoperability that directly impact customer PPA targets\nInfluence industry standards and customer roadmaps through deep technical engagement and thought leadership in IP subsystem architecture\nWho You Are\nYou can take a vague product requirement and turn it into a subsystem architecture that actually works, not just on paper but through bring-up, without creating downstream chaos for implementation or verification teams\nYou know how to make the hard tradeoff calls between performance, power, and area when the math does not give you a clean answer, and you can explain your reasoning to a VP in two minutes without losing the technical nuance\nYou are the person teams come to when a subsystem integration is not behaving as expected, because you can move between protocol-level details, dataflow analysis, and system-level constraints without losing the thread\nYou do not wait for perfect information to move forward, you build models, run scenarios, and de-risk the architecture early so the team can execute with confidence\nYou mentor without micromanaging, you help engineers think through architectural problems rather than just handing them answers\nYou stay current on industry trends, new protocols, and emerging SoC architectures because you know that what worked five years ago will not cut it for the next generation of products\nThe Team You'll Be Part Of\nYou will join the Digital IP Subsystems Team at Synopsys, a global group responsible for delivering industry-leading silicon IP and subsystem solutions that power self-driving cars, AI accelerators, 5G infrastructure, IoT devices, and more. This is a collaborative, cross-functional environment where you will work closely with talented engineers across IP design, SoC architecture, verification, software, and physical implementation. The team values technical depth, clear communication, and a culture of inclusion and creativity where diverse perspectives drive better solutions.\nIf you’re excited to take on new challenges, make an impact, and grow with Synopsys, we’d love to connect!\nLearn more about what we do: https://www.synopsys.com/designware-ip/ip-subsystems.html\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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