{"id":4335764,"url":"https://alion.io/job/synopsys-soc-engineering-engineer-19244","title":"SOC Engineering, Engineer - 19244","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":64,"ghost_share":0.047,"stale_share":0,"repost_share":0.172,"time_to_fill_p50_days":18,"computed_at":"2026-11-15T07:52:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-15T15:20:58Z","employer_posted_date":"2026-11-15","last_verified_at":"2026-11-15T15:20:58Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAbout the job\nAlternate Job Titles\nASIC Verification Engineer/Sr. Engineer\nIP Verification Engineer/Sr. Engineer\nDesign Verification Engineer/Sr. Engineer\nSoC Verification Engineer/Sr. Engineer\nDigital Verification Engineer/Sr. Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in verification knowing that finding the bug before tapeoutis the difference between a product that ships and one that doesn't. You understand that a good testbench is not about coverage numbers on a dashboard,it is about building an environment that stressesthe design in ways that matter. You think in corner cases. When someone describes a new protocol feature, you are already mentally mapping the sequences that will break it.\nYou are comfortable working in System Verilog and UVM, but you also know when to drop into directed tests because constrained random is missing something specific. Debugging does not frustrate you,it energizes you. You will spend hours in waveforms tracing a signal across clock domains because you know that is where the real work happens.\nYou ask the right questions, align on what needs verification, and move forward even when the spec is still being written. At Synopsys, you will work on IP that powers everything from AI accelerators to autonomous vehicles.\nWhat You'll Be Doing\nDefine block and subsystem verification plans that map directly to design specifications and protocol requirements\nBuild UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors\nWrite constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios\nDebug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues\nCollaborate with RTL designers and global verification engineers to alignon design intent and coverage goals\nApply formal verification techniques to prove properties and close coverage gaps\nDrive verification closure by tracking coverage metrics and iterating on test plans until signoff\nThe Impact You Will Have\nYour verification work determines whether IP blocks integrate cleanly into customer SoCs or require costly respins\nYou will close critical coverage gaps that prevent silicon bugs from reaching production\nThe testbenches you build will be reused across multiple IP releases, multiplying your impact\nYour collaboration with designers will catch issues early, reducing debug cycles and accelerating tapeout\nYou will help establish verification best practices for a newly formed team in Ho Chi Minh City\nThe IP you verify will enable next generation AI, 5G, HPC, and automotive systems used worldwide\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science or related fileds\n0-4 years of hands-on design verification experience in the semiconductor industry\nProficiency in System Verilog and UVM for building testbenches and implementing coverage\nKnowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR\nExperience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems\nSolid scripting skills in Python, Perl, or Tclfor automation and regression management\nWho You Are\nYou can take a protocol spec and translate it into a verification plan that covers what matters, not just what is easy to test\nWhen a regression fails before a milestone, you dig into the waveform and find the root cause instead of waiting for triage\nYou communicate clearly with RTL designers about what you found and what needs to change, without blame\nYou manage multiple verification tasks in parallel without losing track of coverage goals or debug priorities\nYou ask questions when something in the design does not make sense, and you do not assume someone else will catch it\nThe Team You'll Be Part Of\nYou will join the Subsystem Verification Team, IPA groupin Ho Chi Minh City, District 7, working on high-speed silicon-proven interface IP solutions. This team is part of Synopsys' global IP organization and collaborates closely with RTL designers, architects, and verification engineers across multiple sites.\nInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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