{"id":1311239,"url":"https://alion.io/job/synopsys-soc-engineering-manager-18846","title":"SOC Engineering, Manager - 18846","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":110,"ghost_share":0.027,"stale_share":0,"repost_share":0.164,"time_to_fill_p50_days":4,"computed_at":"2026-09-26T05:45:00Z"}},"role":"Security","role_family":"Security","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":34000,"max_usd":77000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1098},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys SpyGlass","optional":false}],"status":"live","first_seen_at":"2026-09-26T16:23:53Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-09-26T19:50:00Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nJob Title:\nSoC RTL Design - Sr Staff\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years building and signing off RTL that actually ships in silicon, not just passes simulation. The difference between a design that tapes out clean and one that comes back with a respin is usually a clock domain crossing someone missed or a constraint someone wrote too loosely, and you are the engineer who catches those things before they become problems. You know that static checks are not checkbox exercises, they are conversations with the design, and you have learned to read what Spyglass is actually telling you beneath the noise.\nYou have debugged enough CDC violations to know which ones matter and which ones are artifacts of tool setup. You have written enough SDC to know when a constraint is fighting the architecture instead of describing it. Running synthesis is not a handoff for you, it is part of how you validate that your RTL decisions were sound. You do not need someone to tell you what good looks like, you have a point of view on design quality and you are comfortable defending it in a review.\nWorking across IP integration, subsystem assembly, and full SoC builds does not intimidate you. You have done it before, and you know how to move between abstraction levels without losing sight of what actually has to work in the end.\nWhat You'll Be Doing\nRun RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs\nDevelop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture\nExecute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff\nPerform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs\nIntegrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols\nCreate and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines\nCollaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout\nThe Impact You Will Have\nYour signoff rigor directly reduces respin risk for customers building chips in advanced nodes where a single CDC bug can cost months and millions\nThe constraints you write become the foundation for physical implementation teams to close timing, making or breaking their ability to meet PPA targets\nYour synthesis validation catches architectural mismatches early, preventing costly surprises downstream in place and route\nThe IP integrations you deliver enable startups and tier-one customers to meet aggressive tapeout schedules with confidence in design quality\nYour expertise in static verification tools shapes internal methodology, raising the bar for what clean RTL means across the System Solutions Group\nThe RTL you design and integrate becomes part of production SoCs powering AI, automotive, 5G, and IoT applications in the field\nYour work helps Synopsys customers tape out some of the most complex and challenging semiconductor designs in the industry\nWhat You'll Need\nBachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification\nProven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis on complex digital designs\nStrong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks\nHands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking\nSolid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls that lead to metastability or functional failures\nExperience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues\nFamiliarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and design flows is a strong plus\nWho You Are\nYou can look at a CDC report with 500 violations and know within an hour which ten actually need fixing and which are tool noise or acceptable design choices\nYou write constraints that implementation teams can actually use, not overly conservative SDC that makes timing impossible or loose constraints that let real problems slip through\nYou push back when an architecture decision is going to create a signoff nightmare three months later, and you do it with enough specificity that people listen\nYou are comfortable working with customers directly, translating their requirements into RTL decisions without needing everything spelled out in a specification\nYou stay current on what good RTL practice looks like as nodes shrink and design complexity grows, and you bring that knowledge into reviews and mentoring\nYou can context-switch between a 10-gate glue logic fix and a multi-thousand-line subsystem integration without losing attention to detail on either\nThe Team You'll Be Part Of\nYou will join the System Solutions Group, a team of specialists in Synopsys technologies who deliver architecture, design, verification, implementation, tools, and methodology to help customers complete their most challenging SoC projects. The work spans from sub-blocks to full turnkey SoCs, and customers range from startups to industry leaders across commercial and government sectors. This is a global team working on real production designs that tape out and ship in silicon.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.","description_format":"text","description_chars":6819,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-26T16:23:53Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":4,"reasons":["conf:6","win:early","comp:brand"],"computed_at":"2026-09-27T02:42:51Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-soc-engineering-manager-18846","json_url":"https://alion.io/job/synopsys-soc-engineering-manager-18846.json","meta":{"generated_at":"2026-09-27T02:42:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":2465,"day_limit":5000,"remaining_today":2535,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}