{"id":4154961,"url":"https://alion.io/job/synopsys-soc-engineering-manager-19527","title":"SOC Engineering, Manager - 19527","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":60,"ghost_share":0.05,"stale_share":0,"repost_share":0.183,"time_to_fill_p50_days":18,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Security","role_family":"Security","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-11-12T10:24:48Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T10:24:48Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nWe Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are\nYou have spent years building and leading teams that deliver subsystems and SoCs that actually ship, not just pass reviews. The difference between a subsystem that integrates cleanly and one that causes months of debug downstream is something you see coming from the architecture phase, and you know how to steer your team away from those cliffs before anyone writes RTL. You are technical enough to review a timing constraint file or debug a CDC violation yourself, but you also know when to step back and let your engineers solve it. Managing remote teams does not intimidate you because you have learned that clarity, trust, and rhythm matter more than proximity. You can sit in a customer call, extract what they actually need from what they say they want, and walk out with a plan your team can execute against. You think in workflows, not just deliverables. Automation, reusable frameworks, and AI-enabled tooling are not buzzwords to you, they are levers you pull to make your team faster and your subsystems more predictable. You push back when a requirement is vague or a timeline does not match reality, and you do it in a way that keeps the relationship intact.\nWhat You'll Be Doing\nLead the architecture, RTL design, integration, and front-end sign-off of DesignWare IP Subsystems from requirements through release\nManage a local engineering team in Bengaluru, driving execution across design, verification, and implementation while coordinating with global stakeholders\nOwn customer communication and requirements translation, ensuring deliverables align with what customers actually need and ship on time\nDrive front-end implementation flows including synthesis timing closure using Fusion Compiler, SpyGlass CDC/RDC checks, low-power architecture, and Formality equivalence checking\nWork hands-on when needed, reviewing RTL, debugging integration issues, authoring verification plans, or resolving critical bottlenecks in the subsystem lifecycle\nChampion AI-enabled methods, workflow automation, and reusable engineering practices to improve team productivity, quality, and cycle time across subsystem programs\nCollaborate across implementation, verification, DFT, and hardening teams to ensure clean handoffs and tape-out readiness\nThe Impact You Will Have\nYour subsystems will integrate into SoCs powering AI, automotive, 5G, and IoT products used by millions of people globally\nYou will shape how Synopsys subsystems are architected and delivered, setting the standard for quality, predictability, and execution velocity\nYour team will deliver subsystems that reduce customer integration risk and accelerate their time to market\nYou will build a culture of automation and reuse that makes every subsequent program faster and more reliable\nYour technical judgment will prevent costly late-stage design issues and keep programs on track through tape-out\nYou will mentor engineers who will go on to lead subsystem and SoC programs themselves\nYour leadership will directly influence the adoption of AI-enabled workflows and modern engineering practices across the IP organization\nWhat You'll Need\nBachelor's or Master's degree in Electronics Engineering or related field with 10+ years of overall experience\n4 to 5 years managing engineering teams, ideally remote or distributed teams, with a track record of on-time delivery\nStrong hands-on ASIC or SoC front-end design experience including RTL design, IP/subsystem integration, and taking designs from architecture through front-end execution\nDeep expertise in at least one or two interface protocols such as AMBA (APB, AXI, CHI), DDR, PCIe, Ethernet, USB, UFS, or UCIe\nExperience with front-end implementation flows including CDC/RDC checks using tools like SpyGlass or VC SpyGlass, UPF and low-power intent, design/timing constraints, and DFT handoff\nProficiency in SystemVerilog, TCL, Perl, or Python for RTL coding, scripting, and automation\nExposure to ASIC tape-out process, ideally at least one or two tape-outs, and understanding of how subsystems move through verification sign-off, DFT insertion, and hardening\nExposure to AI-enabled tools and automation frameworks applied to design, verification, or execution efficiency is a plus\nWho You Are\nYou can extract detailed technical requirements from high-level customer specifications and turn them into executable work packages your team understands\nYou motivate engineers by giving them clarity, autonomy, and air cover when things get messy, not by micromanaging their work\nYou understand verification well enough to evaluate test plans, coverage metrics, and debug strategies even if you are not writing testbenches yourself\nYou can explain a complex timing closure issue or a CDC violation to a customer or executive in two sentences without losing the technical nuance\nYou track progress across multiple moving pieces, five programs, three customers, two tool bring-ups, and you know which one needs your attention today\nYou push for automation and reuse not because it sounds good but because you have seen what happens when teams rebuild the same thing three times\nThe Team You'll Be Part Of\nYou will join the Digital IP Subsystems Team within Synopsys Solutions Group in Bengaluru. This team develops DesignWare IP Subsystem solutions that integrate multiple IP blocks into pre-verified, configurable subsystems, helping customers accelerate SoC development and reduce integration risk. The team works closely with IP design, verification, implementation, and customer engineering teams globally. Your recruiter will share more about the team structure, current programs, and roadmap during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\n\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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