{"id":3615954,"url":"https://alion.io/job/synopsys-soc-engineering-principal-engineer-18621","title":"SOC Engineering, Principal Engineer - 18621","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":65,"ghost_share":0.046,"stale_share":0,"repost_share":0.2,"time_to_fill_p50_days":17,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys IC Validator","optional":false},{"name":"Synopsys PrimePower","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-11-02T16:27:26Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-05T18:32:51Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Description and Requirements\nPlease note: Preferred location is Auston, however alternate locations can be Dallas, Phoenix and Mountain View.\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent over a decade taking complex SoCs from RTL to silicon, and you know that the difference between a chip that meets PPA and one that doesn't often comes down to decisions made during floorplanning or a CTS strategy that accounts for what the foundry PDK will actually give you at 3nm. You are the engineer who sees congestion coming three steps ahead and adjusts before it becomes a crisis that delays tapeout.\nWorking at advanced nodes is not new to you. You have closed timing on multi-billion transistor designs where every picosecond matters and every milliwatt counts. You know when to push the tools harder and when to step back and rethink the approach. Customers trust you because you do not just run flows, you understand why they work and when they won't.\nYou are comfortable leading technical conversations with design teams, applications engineers, and customers who need real answers, not platitudes. Mentoring comes naturally because you remember what it was like to debug your first IR drop violation at 2am before tapeout. At Synopsys, you will work on the hardest physical design problems in the industry, with the tools that define the state of the art, and with customers who are building the next generation of silicon.\nWhat You'll Be Doing\nLead full-chip and block-level physical implementation from RTL through GDSII tapeout on advanced-node designs at 5nm, 3nm, and below\nDefine and execute floorplanning, power planning, placement, clock tree synthesis, routing, and signoff strategies that hit PPA targets\nDrive timing closure, power optimization, congestion reduction, and area improvement using Fusion Compiler, PrimeTime, and StarRC\nPerform and review static timing analysis, ECO implementation, IR-drop analysis, electromigration checks, and physical verification using IC Validator\nWork directly with semiconductor customers to enable their success, troubleshoot design challenges, and deliver technical workshops and methodology guidance\nDevelop automation scripts and flows using Python, Tcl, and shell scripting to improve design productivity and methodology efficiency\nLeverage AI and ML-based physical design technologies including DSO.ai and Fusion Compiler optimizations to accelerate closure and explore the design space\nThe Impact You Will Have\nEnable customer tapeouts on the most advanced process nodes in the industry, directly influencing the success of next-generation AI, mobile, and high-performance computing chips\nEstablish physical design methodologies and best practices that scale across large SoC programs and improve turnaround time for multi-billion transistor designs\nTranslate real-world design challenges into actionable requirements that shape the roadmap for Synopsys implementation and signoff tools\nMentor and elevate junior engineers, building technical depth across the team and raising the bar for design closure strategies\nDeliver designs that meet aggressive PPA targets and tapeout schedules, proving out methodologies that customers will adopt across their portfolios\nDrive automation and flow innovation that reduces manual effort, catches issues earlier, and makes complex physical design more predictable\nInfluence foundry engagement and tool development by surfacing what works and what breaks at the cutting edge of semiconductor technology\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field\n10 to 15+ years of hands-on ASIC or SoC physical design experience with a proven track record of multiple successful tapeouts at advanced process nodes\nDeep expertise in floorplanning, power planning, place and route, clock tree synthesis, timing closure, and physical verification including DRC and LVS\nStrong working knowledge of IR-drop analysis, electromigration analysis, and ECO methodologies for late-stage design fixes\nProficiency in scripting languages including Python, Tcl, Perl, or shell for automation and flow development\nExperience with Synopsys tools such as Fusion Compiler, PrimeTime, IC Validator, StarRC, Formality, and PrimePower is a strong plus\nFamiliarity with foundry technologies from TSMC, Samsung, or Intel and an understanding of what changes at 5nm and below is highly valued\nWho You Are\nYou can walk into a customer meeting, listen to a design problem, and sketch out a viable closure strategy on a whiteboard without needing to run back to the lab first\nWhen a design is failing setup by 200ps two weeks before tapeout, you do not panic, you methodically work the problem, prioritize the right fixes, and communicate progress clearly to stakeholders\nYou have a point of view on methodology and you are not afraid to push back when a flow does not make sense or a customer request will create more problems than it solves\nMentoring is something you do because you care, not because it is on a performance review, and junior engineers leave conversations with you with a clearer picture of what to do next\nYou are organized enough to juggle multiple tapeout schedules, customer engagements, and internal projects without dropping threads or losing track of what matters most\nYou write automation that other engineers actually use because it solves a real problem and does not require a PhD to understand\nThe Team You'll Be Part Of\nYour recruiter will share more about the team structure and mission during the interview process.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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