{"id":1961123,"url":"https://alion.io/job/synopsys-soc-engineering-principal-engineer-18999","title":"SOC Engineering, Principal Engineer - 18999","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":168000,"max_usd":321000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":542},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-06T15:22:18Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-13T17:19:13Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years turning complex system requirements into working silicon, and you know that the hardest part is not writing RTL, it is making the right architectural decisions in week two that keep your team from hitting a wall in month six. You have led design teams through the full cycle, from early partitioning conversations to timing closure, and you understand that leadership at this level means knowing when to dive into the details and when to step back and let your engineers solve it.\nYou are the engineer who can sit with a customer discussing SoC requirements and walk out with a micro-architecture that your team can actually build. Ambiguity does not slow you down. You ask the right questions, make decisions with incomplete information, and adjust as new constraints emerge. You have debugged enough CDC violations and timing paths to know what good RTL looks like before it even hits synthesis.\nYou care about the people you lead. Not in a vague mentorship way, but in the practical sense of unblocking a senior engineer stuck on a clock domain crossing issue or helping a junior designer understand why their FSM will not synthesize cleanly. At Synopsys, you will work on real customer designs that ship in high-performance computing, automotive, and aerospace systems, leading teams that build ASICs and FPGAs that actually matter.\nWhat You'll Be Doing\nLead design teams of junior and senior engineers through full ASIC and FPGA development cycles, from specification to GDSII handoff\nPartition and architect complex SOC designs from customer requirements, creating high-level and micro-architectures that balance performance, area, and power\nDrive RTL development using SystemVerilog, ensuring designs meet quality standards through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness\nCollaborate directly with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements\nImplement complex industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SOC designs\nDevelop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff\nWork hands-on with customers ranging from startups to industry leaders across automotive, aerospace, defense, and high-performance computing markets\nThe Impact You Will Have\nYour architectural decisions will directly determine whether customer designs meet aggressive PPA targets in advanced process nodes\nThe teams you build and lead will deliver turnkey SOC designs that power next-generation AI, autonomous vehicles, and mission-critical aerospace systems\nYour design methodologies will become reusable frameworks that accelerate future customer engagements across the Solutions group\nThe RTL quality standards you enforce will reduce verification cycles and prevent costly respins for multi-million-dollar tape-outs\nYour ability to navigate complex customer requirements will unlock new business opportunities and long-term partnerships\nThe engineers you mentor will grow into technical leaders who carry forward the rigor and craft you bring to every design\nYour work will help Synopsys customers ship products faster, with higher confidence, in markets where failure is not an option\nWhat You'll Need\nBachelor's degree in Electrical Engineering or Computer Engineering\n15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases\nProven experience leading design teams, including mentoring engineers and managing technical execution across project milestones\nDeep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical design handoff\nStrong SystemVerilog RTL coding skills with demonstrated ability to design and review complex control and datapath logic\nWorking knowledge of industry-standard protocols such as PCIe, Ethernet, or UCIe in real production designs\nExperience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms\nWho You Are\nYou can explain a complex clock domain crossing issue to a junior engineer in a way that makes them understand the underlying problem, not just the fix\nYou have strong opinions on RTL coding style and design partitioning, and you can defend them with specific examples from designs you have shipped\nYou are comfortable pushing back on a customer requirement when the architecture does not make sense, and you can propose a better solution that still meets their goals\nYou move between leading strategy conversations and debugging synthesis warnings without losing context or momentum\nYou treat code reviews as teaching moments, not checklists, and your feedback makes engineers better at their craft\nYou know when a design is ready to move forward and when it needs another iteration, and you are not afraid to make that call even under schedule pressure\nThe Team You'll Be Part Of\nYou will join the Synopsys Solutions group, a team that delivers end-to-end SOC design services to customers across high-performance computing, automotive, aerospace, and defense markets. Your team works on full turnkey designs from specification to silicon, partnering with customers that range from startups to industry leaders and government agencies. You will collaborate closely with verification, DFT, and physical design teams, and you will have access to the full Synopsys EDA toolset and IP portfolio to solve customer challenges.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. 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