{"id":3805889,"url":"https://alion.io/job/synopsys-soc-engineering-principal-engineer-19276","title":"SOC Engineering, Principal Engineer - 19276","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":99,"open_postings":64,"ghost_share":0.047,"stale_share":0,"repost_share":0.188,"time_to_fill_p50_days":18,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Embedded C","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"C","optional":true},{"name":"Synopsys VC Formal","optional":true},{"name":"Synopsys VCS","optional":true},{"name":"Synopsys Verdi","optional":true}],"status":"live","first_seen_at":"2026-11-05T13:19:08Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-08T19:57:57Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou are a hands-on verification leader who translates complex architectural and system requirements into executable verification plans and measurable sign-off criteria. You understand that the hardest integration bugs often emerge from interactions between processors, interconnects, memory, firmware, and system-control logic.\nYou combine technical leadership with practical execution. You can architect a UVM environment, debug a processor boot failure, investigate an interrupt or power-sequencing issue, and guide engineers through coverage closure. You distinguish RTL defects from testbench, software, configuration, and specification issues, and drive them toward resolution.\nYou lead with clear priorities and technical credibility. You work directly with customers and cross-functional teams, communicate risks early, and make evidence-based readiness decisions. Your architectural understanding and reusable verification skills allow you to contribute across different subsystem functions and full-chip engagements.\nWhat You’ll Be Doing\nLead subsystem and SoC verification from requirements review and planning through environment development, regression execution, coverage closure, and sign-off.\nTranslate specifications into verification plans, test scenarios, coverage models, checkers, and traceable acceptance criteria.\nArchitect reusable SystemVerilog/UVM environments integrating commercial VIP, processor models, register models, assertions, reference models, and scoreboards.\nVerify processor and system integration, including boot flows, address mapping, memory access, coherency, interrupts, timers, debug, and configuration interfaces.\nDrive verification of clock switching and gating, reset sequencing, power-state transitions, isolation, retention, and cross-domain dependencies.\nVerify fault-management and recovery behavior, including error capture, masking, aggregation, ECC/parity, watchdogs, monitors, and error injection.\nDevelop directed, constrained-random, and embedded C tests covering concurrent traffic, corner cases, initialization, and failure/recovery sequences.\nLead root-cause debug across RTL, verification environments, firmware, and third-party IP; coordinate fixes and verify resolution.\nOwn regression health, defect tracking, requirements traceability, functional/code coverage, milestone readiness, and sign-off evidence.\nMentor engineers and coordinate technical execution with architecture, design, firmware, formal verification, and other engineering teams.\nThe Impact You Will Have\nIdentify critical integration and system-level defects before silicon, improving quality and reducing late-stage program risk.\nEstablish clear verification scope and measurable closure criteria that support predictable customer milestones.\nBuild reusable environments and methodologies that accelerate future subsystem and SoC engagements.\nImprove execution efficiency through effective debug, automation, disciplined regressions, and risk-based prioritization.\nStrengthen customer confidence through transparent communication and traceable verification evidence.\nDevelop engineers into independent technical owners and future verification leaders.\nWhat You’ll Need\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.\n15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.\nProven experience leading verification teams and driving technical execution through major milestones and sign-off.\nStrong SystemVerilog/UVM expertise, including constrained-random stimulus, assertions, functional coverage, scoreboards, and register models.\nDeep understanding of processor-based SoC architectures, including multicore integration, memory hierarchy, coherent interconnects, interrupts, boot, and debug.\nHands-on experience verifying clock, reset, and power-control logic, including sequencing, state transitions, dependencies, and recovery behavior.\nExperience verifying hardware fault-management mechanisms, including error reporting, masking, ECC/parity, error injection, and fault recovery.\nWorking knowledge of AMBA interfaces and coherent interconnect protocols, with practical system-level transaction-debug experience.\nEmbedded C/C++ experience for initialization, processor-driven tests, interrupt handling, and hardware/software debug.\nStrong capability in regression management, coverage analysis, requirements traceability, and verification closure.\nExperience with simulation, waveform-debug, and verification-management tools, plus scripting in Python, Tcl, or shell.\nStrong communication skills and experience working with customers and geographically distributed teams.\nPreferred Qualifications\nLow-power verification using UPF and power-aware simulation.\nLockstep verification and requirements-based verification for safety-critical designs.\nFormal verification and assertion-based verification experience.\n Emulation experience, including platform bring-up, software-driven testing, or simulation-to-emulation test reuse, is a plus.\nExperience with Synopsys VCS, Verdi, VC Formal, and verification-management tools.\nWho You Are\nYou identify missing scenarios in a verification plan and explain the resulting product risk.\nYou move comfortably between technical planning, environment reviews, and hands-on debug.\nYou challenge ambiguous requirements constructively and establish agreement on expected behavior.\nYou give engineers clear ownership while remaining accountable for integration and delivery.\nYou assess readiness using passing tests, coverage, and defect evidence rather than activity alone.\nYou make sound sign-off recommendations under schedule pressure and communicate unresolved risks clearly.\nThe Team You’ll Be Part Of\nYou will join the Synopsys Solutions group, delivering end-to-end SoC and subsystem engineering services across diverse customer programs. You will collaborate with architecture, RTL design, firmware, verification, DFT, and physical design teams. Your responsibilities may span different subsystem functions and full-chip engagements, providing opportunities to apply your technical leadership across architectures and markets.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.\nIn addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.","description_format":"text","description_chars":7811,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-05T13:19:08Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 178 · green card filings: 177","filings_12m":178,"filings_prev_12m":208,"green_card_filings_12m":177,"median_offered_wage_usd":157472,"route":null,"cap_exempt":false,"checked_at":"2026-11-08T10:45:15+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":61}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":2,"expected_fill_days":18,"reasons":["conf:2","velocity","win:early","comp:brand"],"computed_at":"2026-11-08T05:47:12Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-soc-engineering-principal-engineer-19276","json_url":"https://alion.io/job/synopsys-soc-engineering-principal-engineer-19276.json","meta":{"generated_at":"2026-11-08T21:54:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":45680,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-soc-engineering-principal-engineer-19276"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-soc-engineering-principal-engineer-19276"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-soc-engineering-principal-engineer-19276"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-soc-engineering-principal-engineer-19276\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-soc-engineering-principal-engineer-19276"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3805889}},{"tool":"search_jobs","arguments":{"company":"synopsys.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3805889},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}