{"id":1950240,"url":"https://alion.io/job/synopsys-soc-engineering-sr-staff-engineer-19120","title":"SOC Engineering, Sr Staff Engineer - 19120","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":87,"ghost_share":0.034,"stale_share":0,"repost_share":0.184,"time_to_fill_p50_days":12,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":52000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimePower","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-10-06T09:38:49Z","employer_posted_date":"2026-10-06","last_verified_at":"2026-10-13T21:25:10Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence-from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams.\nYou have solid experience across the timing closure lifecycle-constraints development and validation, STA signoff, power analysis, and ECO support-and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl).\nWhat You’ll Be Doing:\nOwn and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.\nPerform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams.\nDevelop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.\nRun and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.\nSupport timing and power ECO generation, and validate fixes through signoff checks and regressions.\nWork with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).\nUse Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.\nBuild/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.\nContribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.\nThe Impact You Will Have:\nEnable predictable and high-quality timing closure for high-performance, low-power silicon.\nImprove first-pass success through robust constraints, clean signoff, and disciplined closure practices.\nStrengthen team execution by contributing to repeatable STA flows, automation, and cross-team alignment.\nSupport successful project milestones through timely analysis, crisp communication, and ownership of deliverables.\nWhat You’ll Need:\nBachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.\n8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).\nStrong hands-on experience in:\nConstraints development/validation (SDC)\nSTA signoff across modes/corners, including MMMC concepts\nTiming closure debugging and ECO validation\nPower analysis/support (PrimePower / PT-PX exposure preferred)\nProficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).\nWorking knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).\nStrong scripting skills in TCL (required) and Python/Perl (preferred).\nUnderstanding of low-power and high-frequency design considerations (UPF awareness is a plus).\nWho You Are:\nSelf-driven, accountable, and comfortable working with minimal supervision on defined deliverables.\nStrong analytical and debugging skills with attention to detail.\nClear communicator and effective collaborator across design, PD, and verification.\nOpen to learning, improving flows, and sharing knowledge within the team.\nThe Team You’ll Be A Part Of:\nYou’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement-working closely with experts across domains to help customers achieve their silicon goals.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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