{"id":2728897,"url":"https://alion.io/job/synopsys-soc-engineering-staff-engineer-18282","title":"SOC Engineering, Staff Engineer - 18282","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":80,"ghost_share":0.038,"stale_share":0,"repost_share":0.188,"time_to_fill_p50_days":14,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":50000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":557},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-10-16T17:18:15Z","employer_posted_date":"2026-10-16","last_verified_at":"2026-10-17T15:11:16Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nAlternate Job Titles\nPhysical Design Engineer (Senior/Staff)\nPlace and Route Engineer (Senior/Staff)\nSOC Physical Implementation Engineer\nBackend Design Engineer (Senior/Staff)\nASIC Physical Design Engineer\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years in physical design where routing decisions determine whether a chip tapes out clean or burns weeks in ECO. You know Fusion Compiler or ICC2 from debugging congestion hotspots and timing violations at 2am, not from training slides. P&R is equal parts science and pattern recognition, and you have developed both.\nYou do not wait for a perfect floorplan. You flag what will break and propose something workable before it becomes a schedule problem. When extraction results look wrong, you dig until you understand why. The best solutions often come from walking to the frontend team and asking the right question.\nMentorship matters to you. You remember staring at a million DRC violations as a junior engineer, so you take time to show someone how to read a timing report or why their power grid will not close. You script your way out of repetitive work in TCL or PERL, and you know when automation helps versus when manual is faster.\nAt Synopsys, you will work on real SOC designs using the tools the industry depends on. The problems are hard, the work is real, and what you build will matter.\nWhat You'll Be Doing\nOwn physical implementation using Fusion Compiler or ICC2, from floorplanning through routing and signoff closure\nDebug complex P&R issues including timing, congestion, IR drop, and physical verification failures across hierarchical designs\nGuide customer design and CAD teams on tool usage, methodology, and design closure as a trusted technical advisor\nDevelop physical design flows and automation scripts in TCL, PERL, or Python to improve efficiency\nWork with Synopsys BU and Sales teams to deploy tool and IP solutions that solve real customer problems\nMentor junior engineers on P&R fundamentals, debugging techniques, and tool best practices\nThe Impact You Will Have\nAccelerate customer tapeout schedules by solving physical design bottlenecks that would otherwise cause weeks of delay\nImprove Synopsys physical design methodologies through real-world deployment and customer feedback\nEnable successful Fusion Compiler and ICC2 adoption across customer teams, directly influencing tool ROI\nReduce design respins by catching physical implementation problems early in the flow\nBuild long-term team capability by elevating junior engineer skills and reducing external support dependency\nShape EDA tool development by surfacing customer pain points that matter\nContribute to silicon products powering AI, automotive, mobile, and data center applications worldwide\nWhat You'll Need\nBachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or equivalent\n3 to 6+ years hands-on Place and Route experience using Fusion Compiler or ICC2 on complex SOC or ASIC designs\nStrong knowledge of P&R, extraction, static timing analysis, IR drop, and physical verification fundamentals\nProficiency in TCL, PERL, or Python scripting for automation and flow development\nSolid debugging skills to trace root causes across timing, power, signal integrity, and DRC/LVS domains\nExperience with signoff tools like PrimeTime, Redhawk, StarRC, or ICV is a plus\nEffective English communication skills for customer-facing and cross-functional work\nWho You Are\nYou explain complex timing paths or IR drop issues to customers in ways that clarify tradeoffs, not just symptoms\nYou work independently on ambiguous problems but escalate before issues become crises\nYou treat mentorship as part of the job and genuinely want junior engineers to succeed\nYou stay organized across multiple projects without letting details slip when priorities shift\nYou read release notes, try new features, and give real feedback instead of just complaining\nYou collaborate naturally with customer CAD leads, BU engineers, and Sales teams\nThe Team You'll Be Part Of\nYou will join the SOC Engineering team in Ho Chi Minh City, focused on developing and implementing advanced SOC designs using Synopsys EDA tools and IP. This team works closely with Business Units and Sales to deliver turnkey projects and customer-facing technical advisory services across the full design cycle from architecture through post-silicon validation.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. 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