{"id":119497,"url":"https://alion.io/job/synopsys-synopsys-12","title":"ASIC Physical Design, Sr Staff Engineer - 16724","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":76,"ghost_share":0.039,"stale_share":0,"repost_share":0.171,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":94000,"max_usd":161000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-08-24T20:33:16Z","employer_posted_date":"2026-09-14","last_verified_at":"2026-10-22T16:34:25Z","board_verified":true,"closed_at":null,"days_open":58,"trust":{"level":"ghost","repost_count":3,"flags":["repost"],"days_open":58},"description":"Job Description and Requirements\nWe Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.\nYou Are:\nYou are an experienced ASIC Physical Design Engineer with a passion for innovation and a proven track record in complex SoC and test chip implementations. You thrive in collaborative environments, excel at cross-functional teamwork, and are ready to lead technical execution on advanced process nodes. Your expertise in the physical design flow and familiarity with industry-leading tools make you a valuable contributor to our mission of delivering robust, silicon-proven IP solutions.\nWhat You’ll Be Doing:\nContributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.\nDeveloping overall floorplan and power/ground strategies tailored for diverse test chip architectures.\nOwning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.\nExecuting and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).\nIntegrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.\nDriving tool flow automation and debugging to enhance productivity and design reliability.\nCollaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.\nPreparing and releasing all supporting views and documentation necessary for tape-out, maintaining mask tooling forms and checklists on foundry portals.\nThe Impact You Will Have:\nEnable robust validation of Synopsys's IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.\nAccelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.\nEnhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.\nBolster Synopsys's reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.\nFoster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.\nChampion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.\nWhat You’ll Need:\n9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.\nDeep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.\nFamiliarity with IP integration, test chip methodology, and advanced verification flows.\nProficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.\nExperience coordinating complex, cross-functional projects and leading technical execution.\nAuthorization to work in the USA.\nWho You Are:\nAnalytical thinker with strong problem-solving skills and attention to detail.\nEffective communicator, able to articulate complex technical concepts to diverse stakeholders.\nCollaborative team player, fostering a culture of inclusion and innovation.\nProactive leader, driving continuous improvement and embracing new technologies.\nAdaptable and resilient, thriving in fast-paced, dynamic environments.\nCommitted to excellence and quality in every aspect of design and delivery.\nThe Team You’ll Be A Part Of:\nYou’ll join the Test Chip PHY development team within Synopsys’s Silicon IP business. This group is dedicated to integrating and validating Synopsys’s broad portfolio of IP blocks-logic, memory, interfaces, analog, security, and embedded processors-into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. 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