{"id":1515513,"url":"https://alion.io/job/synopsys-system-level-test-engineer-18758","title":"System Level Test Engineer - 18758","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":96,"ghost_share":0.031,"stale_share":0,"repost_share":0.156,"time_to_fill_p50_days":7,"computed_at":"2026-10-01T05:45:00Z"}},"role":"DevOps","role_family":"DevOps","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":74000,"max_usd":177000,"period":"year","method":"role_country_seniority_unknown","sample_n":196},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"BERT","optional":false},{"name":"GitLab","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-30T09:23:48Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-01T10:46:24Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nWe are seeking a System Level Test Engineerto own system-level silicon validation of DDR, LPDDR, and HBM memory interface IP in the lab. You bring upsilicon, prove training, interoperability, and JEDEC timing across DRAM and HBM devices, and characterize margins at speed.\nThis is a hands-on technical role for someone who is equally comfortable with oscilloscope/VNA/BERT measurements, board-level design tradeoffs, and building automation to scale validation across PVT corners and product generations.\nWhat You'll Be Doing\nPlan and execute system-level validation of DDR, LPDDR, and HBM IP on silicon, covering controller, PHY, and the attached memory device.\nBring up new silicon and reference platforms: power, clocks, reset, training, link-up, and first read/write traffic for Protocol as the program requires.\nCharacterize data eye, setup/hold, CA and DQ timing, voltage-frequency shmoo, and thermal corners. Call out what meets JEDEC or the IP spec, what is marginal, and what fails.\nDebug failures with oscilloscopes, logic or protocol analyzers, and on-chip status: training logs, error counters, and PHY or controller registers. \nSeparate silicon, package, interposer or board, DRAM or HBM device, firmware, and test-setup causes.\nAutomate Pipelines using Gitlab to speed up the Characterization and debug process.\nWrite validation plans, test reports, and bug or errata entries that design and verification can reproduce. Track issues to closure across silicon spins.\nSupport customer system debug when a DDR, LPDDR, or HBM failure maps back to IP behavior, and feed lab findings into the next IP drop and test content.\nKeep golden boards, HBM interposer or substrate setups, instrument configs, and known-good scripts in a state the rest of the lab can reuse.\nThe Impact You Will Have\nYour validation work directly determines whether Synopsys memory IP is ready to ship, affecting product timelines and customer confidence across the semiconductor industry\nThe test automation you build scales across multiple IP products and releases, reducing validation cycle time and increasing coverage\nYour characterization reports become the technical foundation for customer engagements, sales collateral, and internal design reviews\nDebug rigor you bring to silicon issues prevents costly respinsand field failures, protecting both schedule and reputation\nTest methodologies you develop and standardize become the playbook for future validation engineers joining the lab\nCustomer issues you resolve keep high-stakes programs moving, often under tight timelines where your responsiveness is the difference between a delay and a win\nThe data you collect and analyze feeds back into design improvements, tightening the loop between silicon and specification\nWhat You'll Need\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field\n3-5 years in silicon validation, applications, or system-level lab debug of memory interfaces.\nHands-on silicon or board bring-up Experience\nWorking knowledge of DRAM protocol and training: command/address, DQ/DQS or WDQS, ranks, bursts, refresh, and the usual training-fail signatures.\nLab skill with a high-bandwidth oscilloscope, Power Analyzer, BERT, DMM etc.\nScripting that drives the DUT and instruments. Python ispreferred.\nAbility to read JEDEC timing tables, DRAM or HBM datasheets, board or substrate notes, and the IP programming guide, then turn them into a test.\nDebug write-ups that state the failing condition, the evidence, and whether the owner is design, verification, package, board, or the memory vendor.\nSignal-integrity basics on DQ, DQS, and CA: ISI, crosstalk, reflections, probe loading, and how layout or interposer routing works\nInterposer or CoWoS-style assembly constraints, lane repair, temperature gradient across the stack\nWho You Are\nYou can walk into a lab with a failing test case and walk out two hours later with a root cause and a plan, not just a theory\nYou are comfortable presenting technical results to design teams, customers, and leadership, translating measurement data into clear conclusions without losing the nuance\nYou manage multiple validation streams at once, keeping track of what is blocked, what is running, and what needs attention next without dropping threads\nYou do not wait for perfect documentation or a fully defined test plan, you work with what you have, ask the right questions, and start collecting data\nThe Team You'll Be Part Of\nYou will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operatesat the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":5999,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Application Security","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-30T09:23:48Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":7,"reasons":["conf:20","velocity","win:early","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-system-level-test-engineer-18758","json_url":"https://alion.io/job/synopsys-system-level-test-engineer-18758.json","meta":{"generated_at":"2026-10-01T18:54:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1124,"day_limit":5000,"remaining_today":3876,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}