{"id":2550685,"url":"https://alion.io/job/synopsys-validation-verification-engineer-principal-18261","title":"Validation / Verification Engineer, Principal -18261","company":{"id":39954,"name":"Synopsys","domain":"synopsys.com","url":"https://alion.io/company/synopsys-inc","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Avature","truth_index":{"grade":"A","score":100,"open_postings":85,"ghost_share":0.035,"stale_share":0,"repost_share":0.176,"time_to_fill_p50_days":12,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nepean, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":84000,"max_usd":147000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Visual Basic","optional":false}],"status":"live","first_seen_at":"2026-10-14T17:51:02Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-15T05:16:49Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Job Description and Requirements\nWe Are\nSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.\nYou Are\nYou have spent years bringing silicon to life, and you know the moment when a test chip boot is just the beginning. You look at an eye diagram and know whether the problem is in silicon, the firmware, the board, or the test setup, and you do not stop until you know which one. The hardest part of validation is not running the test; it is designing the test that actually tells you something useful.\nYou are comfortable in the lab with an oscilloscope in one hand and a Python script in the other, moving between electrical measurements and data analysis without losing sight of what you are trying to prove. You do not wait for perfect documentation. You work with what you have, ask the right questions, and build the characterization plan that gets the team to release.\nYou push back when a test plan is too shallow or when a root cause analysis stops one layer too early. You have mentored engineers through their first silicon bring-up, and you know how to translate a messy debug session into a clear technical recommendation that design, firmware, and product teams can actually act on.\nWhat You'll Be Doing\nLead first-silicon bring-up and validation for DDR6, DDR5, LPDDR6/X, LPDDR5/5X, MRDIMM, and HBM test chips and evaluation platforms\nDevelop and execute validation plans covering functionality, parametric characterization, margin analysis, and reliability testing across voltage, frequency, process, and temperature corners\nPerform electrical characterization including eye diagram analysis, jitter measurements, timing margins, VREF optimization, power consumption, and signal integrity metrics, correlating silicon results against simulation and design expectations\nDrive systematic debug and root cause analysis of silicon, firmware, board, and test infrastructure issues using lab instrumentation, data analytics, and cross-functional collaboration with design and firmware teams\nBuild automated validation frameworks and reusable test infrastructure using Python, C/C++, and scripting tools to improve efficiency, data collection, and characterization workflows\nLead the development of complex multilayer PCB designs for silicon characterization platforms, validation boards, and customer evaluation kits, including architecture definition, schematic review, component selection, and layout oversight\nGenerate characterization reports, present silicon performance data and debug findings to stakeholders and customers, and maintain validation documentation to support release readiness and customer engagements\nThe Impact You Will Have\nAccelerate time to market for next-generation memory PHY products by driving validation closure and sign-off readiness for DDR6, LPDDR6, HBM, and MRDIMM silicon\nEnsure silicon performance, functionality, and reliability meet design specifications and customer expectations, reducing the risk of field issues and customer escalations\nBuild validation methodologies and automated test frameworks that become the foundation for future product generations and improve team efficiency across programs\nInfluence design and firmware quality by providing data-driven feedback during silicon debug and root cause analysis, catching issues before they reach customers\nEnable customer success by delivering accurate characterization data, supporting issue replication and resolution, and presenting silicon performance with clarity and confidence\nStrengthen team capability by mentoring junior engineers, sharing validation best practices, and leading technical workstreams on major silicon programs\nImprove lab infrastructure and processes through equipment selection, validation database development, and process enhancements that benefit the broader engineering organization\nWhat You'll Need\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Engineering Physics, or related discipline\n6+ years of semiconductor industry experience in silicon validation, characterization, test, or product engineering with proven experience bringing up and validating complex mixed-signal or high-speed interface products\nStrong understanding of DDR/LPDDR/HBM protocols, high-speed interfaces, Interface IP/PHY architectures, and digital and mixed-signal semiconductor design concepts\nExperience in PCB board design & understanding of signal integrity, and power integrity concepts\nHands-on experience with lab instrumentation including oscilloscopes, logic analyzers, power analyzers, SMUs, pattern generators, and Automated Test Equipment (ATE) along with test program generation\nExperience performing statistical analysis, correlation studies, margin analysis, failure analysis, and root cause investigations with the ability to interpret large datasets and drive engineering decisions\nExperience with scripting any programming languages such as MATLAB/ Python/ Visual Basic/ TCL/ PERL as well C/C++ & test automation\nIn-depth understanding of JEDEC, automotive qualification standards and specifications and reliability testing. \nExperience with DDR5, LPDDR6, LPDDR5X, HBM3/HBM4 technologies is a plus.\nWho You Are\nYou drive complex technical problems independently across multiple disciplines without waiting for direction\nYou diagnose whether a failure is silicon, firmware, board, or test setup and make the call quickly\nYou translate technical findings into clear recommendations that design, firmware, and customer teams can act on\nYou mentor junior engineers through their first characterization projects without taking over the work\nYou push back when validation coverage is thin or root cause stops at correlation instead of causation\nYou treat documentation as part of the deliverable, not an afterthought\nThe Team You'll Be Part Of\nYou will join the growing Nepean lab team focused on validating Synopsys' memory interface IP portfolio. This is a hands-on lab environment where you will work closely with firmware and design groups to bring new IP from silicon bring-up through production release. The team operates at the intersection of design intent and real-world silicon behavior, and your work will directly inform product readiness and customer deployments.\nRewards and Benefits\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact .","description_format":"text","description_chars":7233,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Simulation & Digital Twin Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-14T17:51:02Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":12,"reasons":["conf:0","velocity","win:early","comp:brand"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/synopsys-validation-verification-engineer-principal-18261","json_url":"https://alion.io/job/synopsys-validation-verification-engineer-principal-18261.json","meta":{"generated_at":"2026-10-15T08:18:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12654,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39954},"rest":"https://alion.io/mcp/rest/get_company?id=39954"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fsynopsys-validation-verification-engineer-principal-18261"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fsynopsys-validation-verification-engineer-principal-18261"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fsynopsys-validation-verification-engineer-principal-18261"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/synopsys-validation-verification-engineer-principal-18261\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fsynopsys-validation-verification-engineer-principal-18261"}]}