{"id":2600655,"url":"https://alion.io/job/talent-cloud-senior-asic-physical-layout-engineer","title":"Senior ASIC Physical Layout Engineer","company":{"id":4423596,"name":"TalentCloud","domain":"talentcloud.group","url":"https://alion.io/company/talent-cloud-3","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Manatal","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Lausanne, Switzerland"],"countries":["CH"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":105000,"max_usd":240000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1655},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Siemens Calibre","optional":false}],"status":"live","first_seen_at":"2026-10-15T07:59:36Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-15T19:33:01Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Senior ASIC Physical Layout Engineer\n Location: Lausanne Area / Western Switzerland (Flexible working culture)\nPermanent Position\nAre you an experienced Layout Engineer looking to work on cutting-edge mixed-signal ASICs that push the boundaries of ultra-low-power technology?\nI'm currently supporting a highly respected Swiss technology organisation in their search for a Senior ASIC Physical Layout Engineer to join an experienced multidisciplinary IC design team developing next-generation semiconductor solutions.\nThis is an opportunity to work somewhere that combines the technical challenges of advanced R&D with the stability and long-term vision of an established organisation.\nWhat you will be working on\nLead top-level physical layout integration for advanced mixed-signal ASICs\nDrive floorplanning, chip finishing and physical verification through to successful tape-out\nSolve complex DRC/LVS/ERC challenges across advanced CMOS technologies\nCollaborate closely with Analog, RF, Digital and System Designers\nContribute to ultra-low-power SoCs, imaging devices and advanced RF technologies\nHelp shape physical design methodologies and layout best practices\n What we're looking for\nStrong experience delivering full-chip or top-level IC layout\nExpertise with Cadence Virtuoso (Virtuoso XL)\nStrong hands-on experience using Siemens Calibre (DRC/LVS/ERC)\nExperience with mixed-signal, Analog and/or RF ASICs\nKnowledge of advanced CMOS technologies\nProven experience supporting successful tape-outs\nExperience resolving complex LVS issues and top-level integration is highly valued\nStrong English communication skills\nNice to have\nUltra-Low Power (ULP) design\nFinFET technologies\nAdvanced process nodes\nESD / Latch-up expertise\nRF layout optimisation\n Why consider this opportunity?\nWork on genuinely innovative semiconductor technology\nJoin an internationally recognised Swiss engineering organisation\nLong-term permanent position\nCollaborative, highly technical environment\nExcellent work-life balance\nOpportunity to influence future IC development\nRelocation support available for suitable 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