{"id":1230654,"url":"https://alion.io/job/talent-corner-hr-services-design-and-verification-soc-engineer","title":"Design and Verification SoC Engineer","company":{"id":3801171,"name":"Talent Corner HR Services","domain":"talentcorner.in","url":"https://alion.io/company/talent-corner-hr-services","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-18T04:12:58Z","employer_posted_date":null,"last_verified_at":"2026-09-18T04:12:58Z","board_verified":false,"closed_at":null,"days_open":41,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":41},"description":"Job Overview : \n\nWe are looking for an experienced Design and Verification SoC Engineer with 10+ years of experience in SoC/ASIC Design Verification. The ideal candidate should have strong expertise in SystemVerilog, UVM, verification methodologies, testbench development, functional verification, debugging, and coverage closure.\n\nThe candidate will work closely with Design, Architecture, and Verification teams to ensure robust verification of IP, subsystems, and complete SoC designs.\n\nKey Responsibilities : \n\n- Perform SoC and ASIC design verification across IP, subsystem, and SoC levels.\n\n- Develop and maintain verification environments using SystemVerilog and UVM.\n\n- Design, develop, and execute comprehensive verification testbenches and test scenarios.\n\n- Perform functional verification of RTL designs and identify design/verification issues.\n\n- Debug simulation failures and work closely with design teams to resolve issues.\n\n- Drive coverage analysis and coverage closure to ensure verification completeness.\n\n- Apply industry-standard verification methodologies and best practices.\n\n- Work with RTL design teams to understand specifications, architecture, and design intent.\n\n- Participate in verification planning, test development, execution, and sign-off activities.\n\n- Contribute to verification of IP, subsystem, and SoC-level designs.\n\n- Analyze verification results and identify potential design or functional issues.\n\n- Collaborate effectively with Design, Architecture, and Verification teams throughout the development lifecycle.\n\n- Provide technical inputs for improving verification quality, efficiency, and coverage.\n\nRequired Skills : \n\n- 10+ years of experience in SoC/ASIC Design Verification.\n\n- Strong hands-on expertise in SystemVerilog.\n\n- Strong experience with UVM and UVM-based verification environments.\n\n- Hands-on experience in ASIC/SoC verification.\n\n- Strong understanding of verification methodologies and testbench development.\n\n- Experience in functional verification, debugging, and coverage closure.\n\n- Good understanding of RTL design and verification flows.\n\n- Experience in IP, subsystem, and SoC-level verification.\n\n- Strong analytical, problem-solving, and debugging skills.\n\n- Ability to collaborate effectively with Design, Architecture, and Verification teams.\n\nSkills\nUVM, SoC, ASIC, Verification, RTL Design, System Verilog, RTL","description_format":"text","description_chars":2389,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response"],"lifecycle":[{"event":"open","at":"2026-09-25T14:00:00Z"}],"visa":[],"liveness":{"score":23,"band":"cold","label":"Long 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