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Skills: VLSI. Experience: 6 - 8 Years. Qualification: Bachelor Of Engineering\n\nMust-Have**\n(not more than 3-5)\n\n\"We\nare looking for a highly motivated and skilled Design Verification Engineer\nto join our verification team. The ideal candidate should possess strong\nexpertise in SystemVerilog, UVM, AXI, and PCIe protocols, along with solid\nknowledge of verification methodologies and debug techniques.\nThe\ncandidate should also be comfortable leveraging AI tools, prompt engineering,\nand automation techniques to improve verification productivity and accelerate\ndebug cycles.\nThe\nselected candidate will be responsible for developing scalable verification\nenvironments, creating comprehensive verification plans, driving coverage\nclosure, debugging complex issues, and collaborating closely with design,\nfirmware, and architecture teams.\n\n1\n\nVerification Planning & Execution\n\n2\n\nDevelop detailed verification plans based on design and\narchitectural specifications.\n\n3\n\nBuild reusable and scalable verification environments\nusing SystemVerilog and UVM.\n\n4\n\nCreate and execute directed, constrained-random, and\nstress test scenarios.\n\n5\n\nDrive functional, code, assertion, and toggle coverage\nclosure.\n\n6\n\nEnsure high-quality verification sign-off for complex IP\nand SoC subsystems.\n\n7\n\nProtocol Verification\n\n8\n\nVerify industry-standard protocols including:\n\n9\n\nAXI4 / AXI4-Lite / AXI-Stream\n\nRequired\nTechnical Skill Set**\n\nDV with PCIE\n\nDesired\nExperience Range**\n\n6 - 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