Formal Verification Developer

Role: Developer. Skills: VLSI. Experience: 3 - 15 Years. Qualification: Bachelor Of Technology

About the Unit

TCS IAE is redefining the future of industry by embedding

intelligence across engineering, manufacturing, asset, and service value

chains. Powered by AI, connected ecosystems, and autonomous operations, it

transforms insights into action-creating self-optimizing, resilient, and

intelligent enterprises at scale. By seamlessly converging the physical and

digital worlds, TCS IAE is enabling a new era of AI-first enterprises where

systems continuously learn, adapt, and evolve-driving measurable outcomes and shaping

how industries operate for the future.

Role: Formal

Verification Engineer (RTL to Netlist / Netlist to Netlist)

Roles & Responsibilities

·Perform formal equivalence checking (LEC)

between RTL and synthesized netlists

·Perform Netlist-to-Netlist equivalence across

ECO, DFT, low-power, and PnR iterations

·Debug and resolve non-equivalence points (NEPs)

and failing cones

·Handle clock-gating, scan, and DFT-related

equivalence challenges

·Support UPF-aware and low-power formal

verification

·Collaborate with cross-functional teams for

signoff readiness

·Develop scripts and automation to improve formal

verification efficiency

Tools & Skills

·Formal Verification: Synopsys Formality, Cadence

Conformal (LEC / Low Power)

·HDL: Verilog, SystemVerilog

·Low Power: UPF-aware formal verification

·DFT Awareness: Scan logic, clock-gating, test

logic

·Understanding of synthesis, STA, and physical

transformations

·Scripting: Tcl (mandatory), Shell / Python

(preferred)