{"id":3434890,"url":"https://alion.io/job/techbiz-global-dft-post-silicon-validation","title":"DFT & Post-Silicon Validation","company":{"id":3894279,"name":"TechBiz Global","domain":"techbiz.global","url":"https://alion.io/company/techbiz-global","size_band":"11-50","is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":"Join","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"remote","remote_scope":"worldwide","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"inferred","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-09-17T02:19:42Z","employer_posted_date":null,"last_verified_at":"2026-10-29T14:15:45Z","board_verified":false,"closed_at":"2026-10-29T14:15:45Z","days_open":42,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":42},"description":"At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently looking for a \nDFT & Post-Silicon Validation to join one of our clients' team\nAre you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.\nKey Responsibilities\nLeadership & Team Management\n\nLead and mentor the DFT and Post-Silicon engineering teams to drive innovation and efficiency.\n\nProvide technical direction, ensuring alignment with organizational goals.\n\nFoster a culture of continuous improvement and collaboration.\n\nDFT Strategy & Execution\n\nDefine and implement DFT architectures to improve testability, debug capabilities, and manufacturability.\n\nEnsure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.\n\nOptimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.\n\nTest Development & Implementation\n\nDevelop and implement test plans and test strategies at silicon, package, and system levels.\n\nDefine and develop automated test solutions for production and characterization.\n\nEnsure test coverage for all product development stages, from pre-silicon to mass production.\n\nGuarantee high yield on the final solution while considering chiplet complexities.\n\nCross-Functional Collaboration\n\nWork closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.\n\nCollaborate with product management to ensure alignment with customer requirements and timelines.\n\nProcess Improvement & Innovation\n\nContinuously explore and implement new DFT methodologies and manufacturing processes.\n\nLead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.\n\nReporting StructureReports to: Physical Implementation Team Manager\nReceives reports from: DFT and Post-Silicon team members\nRequirements\nBachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.\n\nProven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.\n\nStrong background in post-silicon test optimization and yield analysis.\n\nExperience in defining and implementing test strategies for high-volume production.\n\nProficiency in RTL and testbench development using SystemVerilog and Verilog.\n\nStrong scripting skills (Shell, Tcl, Python3).\n\nHands-on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus.\n\nOriginally posted on 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