{"id":4292923,"url":"https://alion.io/job/tejas-networks-engineer-3","title":"Engineer","company":{"id":9412,"name":"Tejas Networks","domain":"tejasnetworks.com","url":"https://alion.io/company/tejas-networks","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-11-13T11:00:06Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-13T23:59:33Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"We are seeking a passionate, skilled ASIC/FPGA Engineer with specialisations in wireless communications to join our Wireless FPGA team at Tejas Networks and help develop the next generation of RAN hardware. As an Engineer, you will own the FPGA design, Top-level integration of various IP’s, design verification and pre-validation, and provide technical support across RAN software, hardware interfaces, and platform components.\n Design, integrate, verify, and validate the specific IPs for Radio Access Networks (RAN) - 4G, 5G and 6G.\nDevelop and implement testing procedures to ensure quality control and reliability of FPGA-based solutions.\nWork closely with hardware engineers to bring up peripherals and support custom hardware features.\nAnalyse and troubleshoot issues across hardware, firmware, and software layers to ensure system stability and tune the system for performance.\nStay current with wireless communication technologies, standards, and best practices, and apply them to product development.\nMandatory Skills\nBachelor’s degree in electrical engineering, electronics and communication engineering, computer science, or a related field, or equivalent practical experience.\nMinimum 2 years of experience in ASIC/FPGA design and development.\nFirsthand experience in AMD SoC (MPSoC/RFSoC) and Altera FPGA families.\nHands-on experience in building an AI-driven RTL design and verification environment and C++ based/Python based validation setup.\nExpertise in FPGA clocking schemes, timing constraints development and timing closure\nDebug and troubleshoot FPGA designs.\nExperience with high-speed protocols such as 25G Ethernet and PCIe\nExperience with peripherals: I2S, SPI, I2C, eMMC and PMBUS\nGood at documentation and writing technical articles\nDesired Skills\nMaster's degree or PhD in Electrical/Communication Engineering\nExperience with FPGA IP integration and memory system architecture.\nKnowledge of high-performance and low-power design techniques.\nExperience in RF communication systems, Software-defined radio, and related technologies\nExperience in antenna array steering, MIMO systems\nEducation: BE/B.Tech in ECE, ETE, EEE or related fields\nExperience: 0-3 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