{"id":2041803,"url":"https://alion.io/job/teledyne-flir-sr-logic-engineer","title":"Sr. Logic Engineer","company":{"id":176498,"name":"Teledyne FLIR","domain":"flir.com","url":"https://alion.io/company/teledyne-flir","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":82,"ghost_share":0,"stale_share":0.768,"repost_share":0,"time_to_fill_p50_days":41,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":14500,"max_usd":37000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"C++","optional":true},{"name":"CI/CD","optional":true},{"name":"Formal Verification","optional":true},{"name":"Git","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-07T18:06:58Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-10T23:56:49Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Be visionary\nTeledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.\nWe are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins.\nJob Description\nSr. Logic Engineer\nPune, Maharashtra, India | FPGA & High-Speed Protocol Interfaces\nROLE SUMMARY \nWe are seeking a Staff Logic Engineer to architect, implement, and deliver complex FPGA-based logic for high-speed protocol analysis and test systems. The role combines hands-on RTL development, transceiver and interface integration, verification, lab debug, and technical leadership across PCI Express (PCIe), Compute Express Link (CXL), Ethernet, and USB solutions.\nAbout Teledyne LeCroy\nTeledyne LeCroy develops high-performance protocol analysis, test, and measurement solutions used to validate advanced electronic systems. Our engineering teams build hardware and software platforms that help customers bring complex, high-speed technologies to market.\nWhat You Will Do\nFPGA Architecture and RTL Design\nOwn FPGA architecture and microarchitecture for protocol capture, packet processing, filtering, triggering, traffic generation, timestamping, and data movement. \nDesign, implement, and maintain synthesizable RTL using SystemVerilog, Verilog, or VHDL for high-throughput, low-latency datapaths and control logic. \nIntegrate and customize FPGA IP for PCIe, CXL, Ethernet, USB, DDR memory, DMA, and other high-speed interfaces. \nDevelop robust clocking, reset, clock-domain crossing, and data-path schemes across multiple clock domains and transceiver interfaces. \nOptimize designs for timing closure, resource utilization, power, latency, throughput, and design maintainability on large FPGAs. \nHigh-Speed Protocol Interface Development\nDevelop FPGA logic for complex protocol interfaces such as PCIe, CXL, Ethernet, and USB, including packet framing, flow control, error handling, link monitoring, and protocol-aware processing. \nWork with high-speed serial transceivers, reference clocks, equalization controls, link-training behavior, lane alignment, and multi-lane data paths. \nPartner with protocol, hardware, firmware, and software teams to translate specifications and product requirements into implementable FPGA features. \nAnalyze protocol traces and lab measurements to identify interoperability, performance, and corner-case issues. \nVerification, Implementation, and Lab Debug\nCreate design specifications, verification plans, assertions, self-checking simulations, constrained-random tests, and reusable testbench components. \nCollaborate with verification engineers using SystemVerilog/UVM and coverage-driven methodologies; perform block-level and system-level verification. \nExecute synthesis, place-and-route, static timing analysis, CDC/RDC analysis, lint, and design-rule checks; resolve implementation and timing issues. \nDebug FPGA hardware using embedded logic analyzers such as Vivado ILA or SignalTap, protocol analyzers, oscilloscopes, and other lab equipment. \nSupport board bring-up, system integration, regression testing, issue triage, root-cause analysis, and release readiness. \nTechnical Leadership and Collaboration\nProvide technical direction for complex features from concept through production release while remaining deeply hands-on in design and debug. \nLead architecture and RTL reviews, establish coding and verification standards, and drive design quality, reuse, and documentation. \nMentor engineers in FPGA design, timing closure, high-speed interfaces, protocol behavior, and disciplined problem solving. \nCoordinate effectively with cross-functional and geographically distributed teams, including product management, systems engineering, PCB hardware, firmware, software, validation, manufacturing, and customer support. \nCommunicate technical status, risks, tradeoffs, and recommended actions clearly to engineering and program leadership. \nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline. \nTypically 8+ years of relevant digital design experience, with substantial hands-on FPGA development and delivery of production-quality logic. \nExpertise in RTL design with SystemVerilog, Verilog, or VHDL, including synchronous design practices, finite-state machines, pipelining, arbitration, buffering, and error recovery. \nDemonstrated experience with at least two high-speed protocol families among PCIe, CXL, Ethernet, and USB, plus the ability to become effective across the remaining interfaces. \nStrong knowledge of high-speed serial transceivers and FPGA implementation flows on AMD Xilinx UltraScale+/Versal or Intel Stratix/Agilex platforms. \nProven experience with synthesis, constraints, static timing analysis, timing closure, CDC/RDC, reset architecture, and on-chip debug. \nExperience integrating external memory and high-bandwidth data movement, including DDR4/DDR5, DMA, AXI, Avalon, or comparable on-chip buses. \nStrong debugging and analytical skills across RTL simulation, FPGA implementation, board-level behavior, and protocol-level observations. \nAbility to create clear architecture documents, interface specifications, test plans, and engineering documentation. \nEffective written and verbal communication skills and the ability to work from the Pune engineering site in a collaborative product-development environment. \nPreferred Qualifications\nDeep knowledge of PCIe link and transaction layers, LTSSM behavior, equalization, error handling, and protocol analyzer concepts. \nExperience with CXL.io and familiarity with CXL.cache and CXL.mem concepts, coherency-related flows, or CXL compliance and interoperability challenges. \nExperience with Ethernet MAC/PCS/FEC datapaths, multi-rate designs, high-speed SerDes, or packet processing pipelines. \nExperience with USB 3.x/USB4 protocol logic, Type-C related system considerations, or USB protocol analysis and test. \nBackground in protocol analyzers, traffic generators, exercisers, compliance tools, or other test and measurement products. \nExperience with Python, Tcl, C/C++, scripting, continuous integration, automated regression, and source-control workflows such as Git. \nFamiliarity with formal verification, FPGA prototyping, hardware emulation, or advanced performance modeling. \nExperience working directly with customers or field teams to resolve complex interoperability and product issues. \n\nSuccess in This Role\nDeliver scalable FPGA architectures, clean RTL, predictable timing closure, and reliable protocol behavior across demanding high-speed interfaces.\nRaise engineering quality through strong reviews, mentoring, clear decisions, practical risk management, and effective cross-functional execution.\nWork Location\nPune, Maharashtra, India. The position is intended for close collaboration with local and global engineering teams. Specific work arrangements, travel expectations, and employment terms will be discussed during the recruiting process.\nTeledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders. Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.\n.","description_format":"text","description_chars":7704,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","C4ISR","Defense Manufacturing","Video Surveillance"],"lifecycle":[{"event":"open","at":"2026-10-07T18:06:58Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":41,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/teledyne-flir-sr-logic-engineer","json_url":"https://alion.io/job/teledyne-flir-sr-logic-engineer.json","meta":{"generated_at":"2026-10-11T02:52:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":154,"day_limit":5000,"remaining_today":4846,"minute_limit":60,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":176498},"rest":"https://alion.io/mcp/rest/get_company?id=176498"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fteledyne-flir-sr-logic-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fteledyne-flir-sr-logic-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fteledyne-flir-sr-logic-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/teledyne-flir-sr-logic-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fteledyne-flir-sr-logic-engineer"}]}