{"id":104495,"url":"https://alion.io/job/tensordyne-mid-level-asic-design-engineer","title":"Mid Level ASIC Design Engineer","company":{"id":39776,"name":"Tensordyne","domain":"tensordyne.ai","url":"https://alion.io/company/tensordyne","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":19,"ghost_share":0.211,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States","San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":107000,"max_usd":207000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":568},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Multimodal AI","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tokenomics","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-05T23:57:34Z","employer_posted_date":"2026-08-28","last_verified_at":"2026-10-17T17:49:13Z","board_verified":true,"closed_at":null,"days_open":72,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":72},"description":"About Tensordyne\nArtificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Tensordyne is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.\nAbout the role:\nAs a member of Tensordyne’s ASIC team, you will be responsible for the microarchitecture and design implementation of high-performance AI ASICs. These ASICs closely couple novel computational accelerator units, compute, interconnects, networking and 3rd-party IP blocks as needed to redefine the next generation of tokenomics for inference.\nYour responsibilities will be wide-ranging and span at minimum the following:\nResponsibilities:\nWork with architecture on reconciling changes with respect to micro-architecture\nDefine microarchitecture and document\nSelect and integrate 3rd-party IP blocks\nCollaborate with design verification engineers\nRun, analyse frontend synthesis and address all issues\nCollaborate with backend teams on place-and-route guidance and timing closure\nAbility to leverage GenAI usage across all workflows, while retaining ownership and quality of all generated collateral\nRequired Qualifications:\n3+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.\nExperience in IP integration, specifically CPU IP into SoC.\nKnowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation\nFamiliarity with AMBA/APB/AXI Protocol\nFamiliarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....\nHands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.\nFamiliarity with low power design. UPF flow for defining power intent of chips with multiple power domains\nPrevious experience with timing closure at high frequencies is a plus.\nInterest to explore AI architectures for convolution, transformer and other kinds of workloads\nSelf-starter and highly-motivated to work in a dynamic start-up environment.\nB.S. (M.S. preferred) degree in Electrical or Computer engineering.\nTensordyne's culture was built on the following values that are equally important to us as business:\nPut people first. We only succeed when our people succeed.\nEthics and integrity always; Being open, honest, and respectful of everyone.\nThink Big. Be ambitious and have audacious goals.\nAim for excellence. Quality and excellence count in everything we do.\nOwn it and get it done. Results matter!\nMake Each Person Better together than they would be as an individual.\nEmbrace each others’ differences.\nEmbrace that there will be differences.\nTensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.","description_format":"text","description_chars":4324,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-05T23:57:34Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 3","filings_12m":3,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":202500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":3}],"liveness":{"score":17,"band":"cold","label":"Long shot","p_open":1,"p_active":0.483,"p_room":0.35,"age_days":72,"expected_fill_days":30,"reasons":["conf:0","velocity","win:tail"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/tensordyne-mid-level-asic-design-engineer","json_url":"https://alion.io/job/tensordyne-mid-level-asic-design-engineer.json","meta":{"generated_at":"2026-10-17T19:59:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3542,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39776},"rest":"https://alion.io/mcp/rest/get_company?id=39776"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Ftensordyne-mid-level-asic-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Ftensordyne-mid-level-asic-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Ftensordyne-mid-level-asic-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/tensordyne-mid-level-asic-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Ftensordyne-mid-level-asic-design-engineer"}]}