{"id":1216948,"url":"https://alion.io/job/tenstorrent-srstaff-engineer-design-verificationsystem-ip","title":"Sr/Staff Engineer, Design Verification,System IP","company":{"id":48241,"name":"Tenstorrent","domain":"tenstorrent.com","url":"https://alion.io/company/tenstorrent","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":86,"open_postings":76,"ghost_share":0,"stale_share":0.368,"repost_share":0,"time_to_fill_p50_days":75,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-05-25T04:51:44Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-11-01T05:45:39Z","board_verified":true,"closed_at":null,"days_open":160,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":160},"description":"Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.\nWe are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.\nThis role is hybrid, based out of Bangalore, India.\nWe welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.\nWho You Are\nYou have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.\nYou enjoy debugging complex design and verification issues and working closely with cross-functional teams.\nYou’re comfortable building verification environments from scratch and driving coverage closure.\nYou have familiarity with standard bus protocols and modern verification tools.\nWhat We Need\nExperience owning block or subsystem-level verification from test planning to sign-off.\nStrong understanding of constrained-random verification, coverage analysis, and regression debugging.\nFamiliarity with protocols such as AXI, ACE, CHI, or PCIe.\nScripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.\nWhat You Will Learn\nVerification of advanced CPU and memory-management related IPs used in AI/ML systems.\nBuilding scalable UVM environments and improving verification methodologies.\nCollaborating across architecture, RTL, and validation teams throughout the development cycle.\nUsing Automation and AI-assisted tools to improve productivity and debug efficiency\nTenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.\nThis offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. 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