{"id":1643309,"url":"https://alion.io/job/teradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading","title":"ASIC and Logic Design Engineering Manager (Compute Test, North Reading)","company":{"id":58849,"name":"Teradyne","domain":"teradyne.com","url":"https://alion.io/company/teradyne","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":{"grade":"A","score":94,"open_postings":4,"ghost_share":0,"stale_share":0.25,"repost_share":0,"time_to_fill_p50_days":26,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["North Reading, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":170000,"max_usd":314000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":656},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Advantest / Teradyne ATE","optional":false},{"name":"C++","optional":true},{"name":"CI/CD","optional":true},{"name":"Git","optional":true},{"name":"Jira","optional":true},{"name":"Microsoft Project","optional":true},{"name":"UVM","optional":true},{"name":"Verilog","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-09-26T07:00:00Z","employer_posted_date":"2026-09-26","last_verified_at":"2026-11-01T09:15:08Z","board_verified":true,"closed_at":null,"days_open":36,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":36},"description":"We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!\nWe attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.\nOur Purpose\n TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.\nWe cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. \nOpportunity Overview\n The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA’s for Teradyne Compute Test Division’s next generation products. In this role you will lead a team of ~4-6 engineers in a fast-paced environment to help the organization meet key business needs. Requires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products. You should have hands-on experience with complex FPGA (and preferably digital ASIC) SOC designs for real-world products. You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion.\nLead multiple simultaneous (typically 2-3) FPGA or digital IP development projects.\n\nTypically includes oversight of some remote resources.\n\nPlanning and tracking of project schedule and budget.\n\nManage project staffing levels including both full time and contract resources.\n\nRepresent the FPGA team on project core teams and at program reviews.\n\nContribute to FPGA implementation (i.e. code RTL blocks) as needed.\n\nProvide technical support for HW sustaining issues.\n\nSet goals, provide coaching and manage compensation of a 4-6 person team.\n\nContribute to FPGA team process improvement initiatives.\n\nCollaborate with other engineering and business disciplines to ensure that FPGA and IP deliverables satisfy all product requirements.\n\nAll About You\n We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.\nBSEE or MSEE and 12+ years of relevant experience in Digital FPGA design and integration (Digital ASIC experience is a plus). \nMinimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release. \nExtensive experience coding RTL (verilog preferred). \nExtensive experience using digital simulation tools (Cadence preferred). \nExtensive experience using static timing analysis tools. \nExperience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES \nExperience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both. \nExperience using digital design quality tools e.g. LINT, CDC. \nExperience with bug tracking tools (Jira etc.) \nExperience with source control systems (Clearcase, Git, CVS) and continuous integration. \nFamiliarity with digital verification tools and methodologies (preferably UVM). \nExperience with project scheduling tools (e.g. Microsoft project) \nExperience with embedded processors and digital signal processing is a plus. \nExperience with high level programming languages (C, C++) is a plus. \nExcellent presentation and communication skills. \nPreferred: Experience developing hardware for automated test equipment is a plus. \nPreferred: 2-3 years of experience as a first level manager of an engineering team. \nCompensation:\nThe base salary range for this role is $155,500 - $ 248,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.\nIncentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. \nBenefits:\nTeradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.\n#LI-KD1","description_format":"text","description_chars":5158,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":2,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Retirement plans"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Test & Measurement Instruments","Collaborative Robots (Cobots)","Semiconductor Equipment"],"lifecycle":[{"event":"open","at":"2026-10-01T22:41:30Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 40 · green card filings: 21","filings_12m":40,"filings_prev_12m":34,"green_card_filings_12m":21,"median_offered_wage_usd":150943,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":14}],"liveness":{"score":41,"band":"fade","label":"Fading","p_open":1,"p_active":0.748,"p_room":0.55,"age_days":35,"expected_fill_days":26,"reasons":["conf:22","velocity","win:tail","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/teradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading","json_url":"https://alion.io/job/teradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading.json","meta":{"generated_at":"2026-11-01T12:58:07Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20003,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58849},"rest":"https://alion.io/mcp/rest/get_company?id=58849"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fteradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fteradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fteradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/teradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fteradyne-asic-and-logic-design-engineering-manager-compute-test-north-reading"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1643309}},{"tool":"search_jobs","arguments":{"company":"teradyne.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1643309},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}