{"id":4196610,"url":"https://alion.io/job/tessolve-lead-engineer","title":"Lead Engineer","company":{"id":2748975,"name":"Tessolve","domain":"tessolve.com","url":"https://alion.io/company/tessolve","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-11-12T20:35:00Z","employer_posted_date":null,"last_verified_at":"2026-11-12T20:35:00Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are pleased to reach out to you regarding a potential opportunity for the position of Lead Engineer.\n\nJob Description:\nLead and execute memory subsystem and LPDDR validation activities across post-silicon environments.\nDevelop validation strategies, test plans, test cases, and coverage plans for memory controllers, PHY, and LPDDR interfaces.\nPerform LPDDR4/LPDDR4X/LPDDR5/LPDDR5X interface validation, including initialization, training, timing, and functional testing.\nValidate different memory configurations, frequencies, data rates, channels, ranks, and memory densities.\nDebug memory-related failures at SoC, controller, PHY, firmware, and board level.\nWork closely with hardware design teams to understand memory controller, PHY, clocking, reset, power, and interface architecture.\nReview hardware design specifications, block diagrams, schematics, and relevant design documentation.\nSupport silicon bring-up, memory initialization, and platform-level validation.\nDevelop and maintain automation scripts for validation, debug, and data collection using Python, Shell, or similar scripting languages.\nValidate memory reliability, stability, and performance under different system workloads.\nMentor junior engineers and provide technical guidance to the validation team.\nLead technical discussions with internal teams and customers and communicate project status, risks, and dependencies.\n\nExperience:\nStrong experience in memory subsystem validation and debug.\nHands-on experience with LPDDR4/LPDDR4X/LPDDR5/LPDDR5X.\nGood understanding of memory controller architecture, DDR/LPDDR PHY, read/write leveling, memory channels, ranks, and banks, ECC, and memory error handling.\nStrong knowledge of post-silicon validation and silicon bring-up.\nExperience in debugging failures across hardware, firmware, and software layers.\nAbility to read and understand schematics, block diagrams, and hardware specifications.\nGood understanding of system-level interfaces such as PCIe, USB, I2C, SPI, UART, JTAG, etc. is an added advantage.\nUnderstanding of SoC and memory subsystem architecture.\nUnderstanding of memory controller and PHY integration.\nReading and analyzing schematics and board layouts.\nLead a team of validation engineers and own technical deliverables.\nDefine validation priorities, execution plans, and debug strategy, and review test plans, test cases, automation, and debug reports.\nMentor team members on memory validation and hardware debug methodologies.\nGood communication and interpersonal skills.\nSkills\nLPDDR, Lpddr4, Lpddr4X, Lpddr5, Lpddr5X, Python, Shell, Validation","description_format":"text","description_chars":2592,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Embedded & Electronics Design","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-11-12T20:35:00Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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