{"id":1273130,"url":"https://alion.io/job/tessolve-lead-rtl-design-engineer","title":"Lead RTL Design Engineer","company":{"id":2748975,"name":"Tessolve","domain":"tessolve.com","url":"https://alion.io/company/tessolve","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Chennai, India","Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":436},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-28T09:46:24Z","employer_posted_date":null,"last_verified_at":"2026-08-28T09:46:24Z","board_verified":false,"closed_at":null,"days_open":32,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":32},"description":"Job Description :\n\nKey Responsibilities :\n\n- Develop high-quality RTL using Verilog/SystemVerilog based on architecture and design specifications.\n\n- Define and review microarchitecture for complex IPs and SoC subsystems.\n\n- Lead RTL development and ensure quality through coding guidelines and design reviews.\n\n- Integrate IPs into SoC and resolve integration-related issues.\n\n- Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams.\n\n- Perform RTL debugging, lint, CDC/RDC, synthesis, and timing issue analysis.\n\n- Drive design optimization for area, power, and performance (PPA).\n\n- Mentor junior engineers and provide technical leadership.\n\n- Participate in customer discussions, effort estimation, and project planning.\n\nRequired Skills :\n\n- 8 - 15 years of experience in ASIC/SoC RTL Design.\n\n- Strong RTL coding experience using Verilog/SystemVerilog.\n\n- Expertise in Microarchitecture Design.\n\n- Hands-on experience in SoC Integration.\n\n- Good understanding of AMBA protocols (AXI, AHB, APB).\n\n- Experience with Lint, CDC/RDC, Synthesis, and STA concepts.\n\n- Strong debugging and problem-solving skills.\n\n- Familiarity with Git/Perforce and scripting (Python/Perl/Shell) is an added advantage.\n\n- Excellent communication and stakeholder management skills.\nSkills\nRTL Design, Verilog, System Verilog, SoC, Physical Design, Synthesis, AMBA, DFT, Verification","description_format":"text","description_chars":1396,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-26T00:07:01Z"}],"liveness":{"score":31,"band":"fade","label":"Fading","p_open":0.6,"p_active":0.679,"p_room":0.75,"age_days":31,"expected_fill_days":32,"reasons":["seen:31","win:late"],"computed_at":"2026-09-29T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/tessolve-lead-rtl-design-engineer","json_url":"https://alion.io/job/tessolve-lead-rtl-design-engineer.json","meta":{"generated_at":"2026-09-30T02:16:50Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1579,"day_limit":5000,"remaining_today":3421,"minute_limit":60,"resets_at":"2026-10-01T00:00:00Z"}}}