Senior RTL Design Engineer
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Salary
≈ $18k – $46k per year (Estimated)
Location
In office (Bengaluru)
Seniority
Senior · 4+ years exp
First seen by Alion on Oct 22, 2026.
Overview
Company
Impact
Profile match
Tessolve is a semiconductor engineering services company offering pre-silicon and post-silicon expertise, from silicon bring-up and testing labs to a turnkey ASIC solution from design to packaged parts. It hires RTL design, validation, DFT and software engineers and employs more than 3,200 people worldwide. The company is headquartered in Bengaluru, India.
Backed by Novo Tellus Capital Partners
Responsibilities:
- Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL.
- Develop micro-architecture specifications.
- Perform RTL simulations and debug logic issues to root cause.
- Collaborate with verification engineers to develop and review test plans and coverage.
Requirements:
- Solid experience in RTL coding using Verilog/SystemVerilog.
Skills
RTL, SystemVerilog, VHDL, Verilog
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