{"id":3791095,"url":"https://alion.io/job/texas-instruments-design-verification-engineer-10","title":"Design Verification Engineer","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":76,"open_postings":208,"ghost_share":0,"stale_share":0.942,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"MATLAB","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Simulink","optional":false},{"name":"Synopsys SpyGlass","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-05T06:28:07Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-07T21:53:22Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"About TI\nTexas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world's brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We're committed to building a better future - from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us - change the world, love your job!\nAbout the Role:\nAre you looking for a career at one of the leading semiconductor companies in the world? Texas Instruments (TI) is looking for a Digital Mixed-Signal (DMS) Design Engineer to join the team of enthusiastic engineers who develop highly complex mixed-signal devices for audio applications with industry-leading performance.\nWe are looking for a motivated and technically strong DMS Engineer to join our Audio Converters product development team. In this role, you will be responsible for the RTL design and implementation of digital blocks within complex mixed-signal audio converter chips. You will work closely with analog design, AMS verification, digital verification, systems and physical design engineers to develop robust, well-verified and silicon-ready digital implementations.\nThis role provides an opportunity to work on challenging digital design problems within a mixed-signal context, implement complex digital algorithms in RTL, understand the interaction between digital and analog domains, and contribute to products from architecture definition through tapeout and silicon bring-up.\nRequired Skills & Qualifications:\nB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related field.\n3-5 years of hands-on experience in digital RTL design using Verilog and/or SystemVerilog.\nStrong digital design fundamentals: FSMs, FIFOs, pipelines, synchronizers, handshaking and arbitration logic.\nSolid understanding of clock domain crossing (CDC) and reset domain crossing (RDC) concepts and design techniques.\nHands-on experience designing and verifying serial interfaces such as SPI, I²C, I²S, PDM or TDM.\nExperience implementing digital filter blocks (CIC, FIR, IIR) or other DSP-oriented digital designs.\nFamiliarity with the RTL-to-GDSII design flow including synthesis, static timing analysis (STA) and sign-off concepts.\nExperience with RTL quality checks including linting (SpyGlass or equivalent) and CDC/RDC analysis tools.\nAbility to read and interpret timing reports and identify RTL-level root causes for timing violations.\nBasic understanding of mixed-signal design concepts: ADC/DAC architectures, signal chains and digital-analog interfaces.\nFamiliarity with scripting languages such as Python, Perl or Tcl for design automation and flow development.\nAdditional preference\n Experience with audio converter products (ADC, DAC, CODEC, Class-D amplifiers) or audio SoC development.\nKnowledge of sigma-delta modulator architectures, oversampling and multi-stage decimation filter design.\nExperience with MATLAB or Simulink for fixed-point modeling or algorithm-to-RTL translation workflows.\nExposure to UVM-based digital verification environments and co-simulation with analog models.\nUnderstanding of DFT concepts including scan architecture, ATPG and design-for-test best practices.\n Having contributed to RTL design from specification through tapeout and first-silicon bring-up.","description_format":"text","description_chars":3514,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Consumer Electronics","Electrical & Electronic Engineering","Semiconductor Manufacturing","Email Security"],"lifecycle":[{"event":"open","at":"2026-11-05T06:42:58Z"}],"visa":[],"liveness":{"score":70,"band":"hot","label":"Hiring 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