{"id":2562860,"url":"https://alion.io/job/texas-instruments-design-verification-engineer-5","title":"Design Verification Engineer","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":80,"open_postings":167,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":8,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17000,"max_usd":43000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence vManager","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-05-21T06:50:47Z","employer_posted_date":"2026-05-21","last_verified_at":"2026-10-18T00:19:30Z","board_verified":true,"closed_at":null,"days_open":149,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":149},"description":"The RADAR product line is a rapidly expanding business within TI, investing to address the fast-growing segment in Industrial & automotive markets. This product line will enable a scalable portfolio using DSP and ARM multi-cores to support high-end applications in ADAS, body & Chassis and in Industrial space. Radar systems process digital information from sources like digital cameras, lasers, radar and other sensors to perform tasks such as lane departure warning or parking assistance. The processed information can be displayed on screens or announced via acoustical warning signals. The system has multifaceted features such as Highprecision ADC, extremely accurate chirp, wide range visibility and Faster scene processing abilities. As a Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of our advanced RADAR products. You will be responsible for the verification of IP, Subsystem (SS), and System-on-Chip (SoC) designs, contributing to the development of robust verification methodologies and strategies.\nResponsibilities:\nComplete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes:\nActive involvement with architecture team during the spec definition phase \nVerification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics \nIP/SS/SOC verification covering functional and Firmware scenarios in RTL/PARTL, GLS/PAGLS modes. \nDV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs \nActive collaboration with cross functional teams -Architecture, RTL, PD, DFT, Systems, Analog, FW and application teams -to enable the Verification goals for IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\nFinal SoC DV signoff based on Regressions, coverage metrics, DV to spec traceability using C and/or SV-UVM adhering to ISO26262 guidelines \n Qualifications:\n5+ years of DV experience in IP/SS/SOC/Post silicon DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations\nSkills:\nExperience in one or more of the following areas: C-based SoC design verification (DV), firmware verification exposure, scripting knowledge (Perl/Python/AI/ML based DV), DV flow ownership for functional/firmware verification, deep understanding of UVM/SystemVerilog, Specman, GLS/PAGLS/CPF/UPF based verification, post-silicon verification, etc.\nThorough knowledge of standard protocols, such as AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, and high-speed interfaces like CSI and Ethernet.\nWork experience in a C-based environment with complex ARM/DSP multi-processor systems, including power-aware simulations, is a significant plus.\nStrong understanding of digital design fundamentals, computer organization and architectures, and bus protocols.\nExcellent debugging skills with Verilog/VHDL designs.\nGood problem-solving skills.\nExperience with Cadence tools (Xcelium/vManager/Formal JG applications/safety simulator) or similar tools/DV flows.\nProficiency in AMS, CDC digital verification, formal verification, and post-silicon verification, along with familiarity with functional safety and cybersecurity processes, would be advantageous.\nEffective communication skills to interact seamlessly with all stakeholders.\nMust be highly focused and committed to achieving project goals.","description_format":"text","description_chars":3554,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-14T21:15:20Z"}],"visa":[],"liveness":{"score":5,"band":"cold","label":"Long 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