{"id":3122687,"url":"https://alion.io/job/texas-instruments-design-verification-engineer-bcp","title":"Design Verification Engineer | BCP","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":75,"open_postings":172,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":22,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Knoxville, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":80000,"max_usd":153000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":664},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys VCS","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-09-25T23:27:43Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-26T19:38:59Z","board_verified":true,"closed_at":null,"days_open":30,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":30},"description":"Change the world. Love your job.\nTexas Instruments is seeking a Design Verification Engineer to join our Analog Power Products organization in Knoxville. In this role, you will develop and execute verification strategies that ensure first-pass silicon success for next-generation analog and mixed-signal ICs across industrial, automotive, and consumer applications.\nAs a Design Verification Engineer, you will work across the full verification cycle - from developing detailed verification plans and building test benches through running coverage regressions, tracking closure, and contributing to continuous improvements in DV methodology - collaborating closely with digital design and systems engineering teams.\nResponsibilities include:\nDevelop detailed verification plans while working closely with the design and system team to ensure first-pass silicon success\nDevelop test benches, tests, and simulations at RTL and gate-level (GLS) for the entire chip\nRun coverage regressions to meet defined coverage goals\nTrack and communicate verification status, issues, and concerns\nWork with regression tools and develop scripts to submit cases for regression analysis\nContribute to continuous improvements for quality and efficiency on DV strategy, tools, methods, and flows\n Minimum requirements:\nBachelor’s degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, or related field\n3+ years of experience in design verification or a related role\nPreferred qualifications:\nExperience with functional verification methodologies including simulation, assertions, and coverage-driven verification\nProficiency in SystemVerilog and UVM-based testbench development\nExperience with Mixed Signal verification a plus\nExperience with System Verilog real number models a plus\nFamiliarity with RTL simulation tools (Cadence Xcelium, Synopsys VCS, or equivalent)\nExperience with gate-level simulation and timing-aware verification flows\nScripting skills for regression automation and verification flow development (Python, Tcl, or Perl)\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\nStrong verbal and written communication skills\nDemonstrated strong interpersonal, analytical, and problem-solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to take the initiative and drive for results","description_format":"text","description_chars":2437,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Analog & Power 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