{"id":4178428,"url":"https://alion.io/job/texas-instruments-design-verification-engineer-mwd","title":"Design Verification Engineer m/w/d","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":77,"open_postings":198,"ghost_share":0,"stale_share":0.914,"repost_share":0,"time_to_fill_p50_days":31,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Freising, Germany"],"countries":["DE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"UVM","optional":false},{"name":"Cadence vManager","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-11-12T10:30:37Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-13T00:40:11Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Change the world. Love your job.\nWhy APP?\nPower is everywhere! The Analog Power Products team designs and develops more than 30,000 products for the industrial, automotive, personal electronics and communications markets. Our solutions cover the entire AC/DC and DC/DC power spectrum and are leading the industry in power density, power consumption, EMI performance, and other performance metrics. Made up of six dynamic business units, APP is at the forefront of industrial and next-generation automotive trends. You will be joining the SR-LVB product line which is located in Freising, Germany and is working in the fields of inductive DCDC converters. We focus on fully integrated buck converters and controllers in the low voltage area (\nAbout the Job\nThe SR-LVB product line is seeking for a highly motivated Verification Engineer (AMS/DMS). As a member of the Verification team, you will be part of ensuring that the devices work according to specification as well as in-system. Verification engineers work together with analog designers, digital designers, system engineers and test engineers. They are involved in the complete project cycle: scheduling tasks in the project planning phase, verifying the implementation in the design phase and supporting the validation, test and qualification team when the silicon is back. In this position you will gain or further enhance your in-depth knowledge of the latest verification methodologies and tools as well as your understanding of analog circuits.\nAs part of your job, you will also get exposure to other roles such as: Digital Design & Analog Design through formal learning, projects and on-the-job development experiences that will help you broaden your knowledge and accelerate your growth and success at TI.\nExample products we have built are TPS62870, TPS62A01, TPS62810, TPS62880\nAs a Verification Engineer, the key responsibilities are the following but not limited to:\nExecute the pre-silicon verification of mixed-signal ICs in an UVM based environment (AMS/DMS)\n\nCollaborate closely with digital/analog designers, applications and system engineers, and manufacturing test to support pre-silicon verification efforts\n\nImplement test-benches to apply stimuli and checks to verify DUT behavior\n\nWrite detailed verification plans to cover project requirements for top-level functionality, and construct test cases exercising the plan\n\nEvaluate system-level use-cases and re-create these in simulation\n\nDevelop and maintain behavioral models (VerilogAMS / WREAL)\n\nReview the digital and analog design to provide guidance on Design for Verification architecture and features during chip development\n\nSimulate RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits, as well as closed-loop simulation with analog behavioral models\n\nActively participate in the development and improvement of the existing verification flow\n\nMinimum Qualifications:\nBachelor or Master’s degree in electrical engineering or equivalent\n\nPreferred Qualifications:\nBackground in design verification languages and methodologies (e.g. Verilog, SystemVerilog, UVM)\n\nExperience in writing verification plans, creating test benches, automating regression test suites, preparing and presenting detailed verification reviews\n\nExperience in debugging AMS simulations, digital RTL and analog schematics\n\nAble to drive the adoption of new methodologies\n\nBasic knowledge of behavioral modeling for analog IPs (VerilogAMS / WREAL)\n\nScripting skills (Ruby, Python, Perl, …)\n\nKnowledge of Cadence tool suite (ncsim, vManager, IMC, …)\n\nDCDC converter knowledge is a plus\n\nOpen personality with strong verbal and written communication skills\n\nHighly self-motivated team player with the ability to collaborate with international and cross-functional teams\n\nStrong analytical and problem-solving skills\n\nAbility to take the initiative and drive for results\n\nStrong English language skills, German is a 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