{"id":3122664,"url":"https://alion.io/job/texas-instruments-pmic-analog-design-engineer","title":"PMIC Analog Design Engineer","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":75,"open_postings":174,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":22,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false}],"status":"live","first_seen_at":"2026-09-23T04:30:58Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-27T16:56:17Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Change the world. Love your job.\nWe are looking for a highly skilled and passionate Analog Designer, with PMIC experience preferred, to partner with senior technical leads to execute PMIC programs, otaking primary ownership of assigned blocks/sub-systems while receiving architectural guidance on system-level decisions. This is a deeply technical, hands-on role - you will be doing circuit design, participating in layout reviews, PEX simulations, analysis leading to architecture decisions, and collaborating with cross-functional experts to deliver successful IPs and Products. Following are the key responsibilities:\nDesign and deliver high-performance analog circuits and blocks needed for power converter circuits - buck, boost, LDO, and charge pump - meeting aggressive targets for power performance, efficiency, and transients.\nContribute towards PMIC system architecture development and execute block-level designs against challenging performance, power, and area specifications.\nOwn technical execution across the full IC design flow: schematic capture, simulation, layout review, post-layout verification, silicon bring-up, and characterization\nServe as primary technical owner for one or more complex blocks, sub-system and converters (with some guidance & support) within multi-block PMIC products\nEnsure design quality, robustness, and reliability through in-depth technical reviews\nCollaborate with internal systems and architecture teams to resolve integration challenges and drive technical closure\nMentor and support junior engineers on design methodology, tools, and best practices\nMinimum requirements:\nBachelor's degree in Electrical Engineering or related field (Master's or PhD preferred)\n4+ years of analog/mixed-signal IC design experience with strong analog fundamentals and design understanding for standard blocks including BGRs, V2Is, Amplifiers, Comparators, Level shifters, Oscillators\nExperience with high-voltage circuit designs and high speed level shifters\nFamiliarity with SOA (Safe Operating Area) & Reliability, Aging sims\nStrong understanding of mismatch effects and device noise, with experience in auto-zeroing, chopping, and statistical analysis\nGood understanding of Control Systems fundamentals, compensation, large signal analysis etc.\nFully proficient and deeply comfortable with standard Power IC design flows end-to-end (Cadence Virtuoso, Spectre)\nWorst-case corner analysis, top-level and Monte Carlo simulation, and post-layout PEX sign-off\nStrong knowledge of BCD and/or advanced CMOS process trade-offs for high-performance Power IC design\nAbility to work independently and drive design related technical decisions with confidence and provide predictable development schedule for blocks & sub-systems based on the specifications, with high quality.\nShould be able to independently explore multiple options and come up with optimum architectures of blocks for given specs and execute with high quality while adhering to the schedules.\nStrong written and verbal communication skills\nPreferred qualifications:\nExperience in designing blocks for PMICs in consumer electronics (mobile, laptops, wearables)\nUnderstanding of one or more converter control architectures: Adaptive/Constant On/Off Time, peak/valley/average current mode control\nHands-on transistor-level design of integrated power FETs, gate drivers, oscillators, bandgap/bias circuits, error amplifiers, and frequency compensation networks\nHigh-efficiency design techniques with focus on performance while minimizing power and area.\nWorking familiarity with multi-rail PMIC SoC integration: power sequencing, UVLO, OCP, OTP, and digital interfaces (I2C, SPI, MIPI I3C)\nExperience in customer-facing technical alignment and specification negotiation\nPhysical layout understanding and key aspects including power routing, grounding, signal integrity, thermal management, and die area optimization\nExposure to Simplis, AMS, or equivalent simulation tools (good to have)\nExperience of full / partial design ownership of Switching Converters, LDOs\nFull-cycle IC design experience: schematic, simulation, layout collaboration, post-layout verification, silicon validation, and characterization\nAbility to independently manage and execute multiple design tasks in parallel on aggressive schedules\nMentoring Junior members and New College Graduates in the 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