{"id":2563009,"url":"https://alion.io/job/texas-instruments-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":36400,"name":"Texas Instruments","domain":"ti.com","url":"https://alion.io/company/texas-instruments","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"B","score":80,"open_postings":154,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":9,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":47000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-22T11:37:04Z","employer_posted_date":"2026-09-22","last_verified_at":"2026-10-15T16:30:11Z","board_verified":true,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"Change the world. Love your job.\nTexas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/Full chip DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis.\nThis includes:\nActive involvement with architecture team during the spec definition phase\nVerification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics\nip/Full chip verification covering functional and firmware scenarios in RTL and GLS.\nDV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM\nActive collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities\n Minimum requirements\nMinimum of 5+ years of experience in Digital Design Verification. with a Bachelor or master’s degree in EE/ECE/CS or related specializations-Excellent debugging skills with SystemVerilog/VHDL/VAMS designs, with understanding of testbench creation for full chip solutions.\n\n Must have good understanding of analog concepts to create behavioral models for Analog IPs in System Verilog, needed for signal chain verification.- Experience in Motor control for BLDC/BSM motor driver devices including commutation, sensor less control and feedback systems are an added advantage.\n\nWell versed with setting up nad debugging, Gate level simulations/Formal verification methodologies.\nGood knowhow of cadence tools for Design verification activities is an advantage.\nPreferred qualifications:\n\nAbility to establish strong relationships with key stakeholders critical to success, both internally and externally\nStrong verbal and written communication skills\nAbility to quickly ramp on new systems and processes\nDemonstrated strong interpersonal, analytical and problem-solving skills\nAbility to work in teams and collaborate effectively with people in different functions\nAbility to take the initiative and drive for results\nStrong time management skills that enable on-time project delivery","description_format":"text","description_chars":2826,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor Manufacturing","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-14T21:15:20Z"}],"visa":[],"liveness":{"score":13,"band":"cold","label":"Long shot","p_open":1,"p_active":0.381,"p_room":0.35,"age_days":22,"expected_fill_days":9,"reasons":["conf:0","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-15T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/texas-instruments-senior-design-verification-engineer","json_url":"https://alion.io/job/texas-instruments-senior-design-verification-engineer.json","meta":{"generated_at":"2026-10-15T19:18:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":29127,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":36400},"rest":"https://alion.io/mcp/rest/get_company?id=36400"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Ftexas-instruments-senior-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Ftexas-instruments-senior-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Ftexas-instruments-senior-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/texas-instruments-senior-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Ftexas-instruments-senior-design-verification-engineer"}]}