{"id":2570161,"url":"https://alion.io/job/tylsemi-design-verification-engineer","title":"Design Verification Engineer","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"B","score":75,"open_postings":20,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-15T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":49000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Git","optional":true},{"name":"OpenAI","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-06-01T07:39:06Z","employer_posted_date":"2026-06-01","last_verified_at":"2026-10-15T14:09:12Z","board_verified":true,"closed_at":null,"days_open":136,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":135},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nTylSemi Solutions Private Limited is looking for a motivated and detail-oriented Design Verification Engineer to join our growing Verification team. In this role, you will contribute to the verification of cutting-edge SoCs and IPs targeting AI, HPC, and Networking applications. You will work closely with experienced verification engineers and architects to develop testbenches, create test scenarios, analyze coverage, and help ensure high-quality silicon delivery.\nThis is an excellent opportunity for engineers who are passionate about digital design, verification methodologies, and next-generation semiconductor technologies.\nWhat You'll Do\nDevelop and execute verification test plans for IPs, subsystems, and SoC components.\nCreate and maintain SystemVerilog/UVM-based verification environments.\nWrite directed and constrained-random test cases to validate design functionality.\nDevelop functional coverage models and assist in coverage closure activities.\nDebug simulation failures and collaborate with design engineers to resolve issues.\nWrite assertions (SVA) to improve design checking and verification quality.\nParticipate in regression execution, result analysis, and reporting.\nSupport IP integration and subsystem-level verification activities.\nLearn and apply industry-standard verification methodologies and best practices.\nContribute to automation scripts for regression, reporting, and verification productivity.\nWork closely with Design, Architecture, and Software teams to understand requirements and verify functionality.\nWhat We're Looking For\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.\n5+ years of experience in Design Verification.\nStrong understanding of digital design fundamentals and computer architecture.\nKnowledge of:\nVerilog/SystemVerilog\nUVM methodology\nSimulation and debugging concepts\nFunctional and code coverage\nBasic scripting (Python, Perl, Shell, or TCL)\n\nFamiliarity with verification tools from Synopsys, Cadence, or Siemens EDA.\nUnderstanding of common bus protocols such as PCIe, CXL, Ethernet, UCIe, DDR protocols,is a plus.\nGood analytical and debugging skills.\nStrong communication and teamwork abilities.\nPreferred Qualifications\nInternship or academic project experience in ASIC/SoC verification.\nExposure to SystemVerilog assertions (SVA).\nKnowledge of constrained-random verification techniques.\nExperience with Python-based automation.\nUnderstanding of AI, HPC, or Networking architectures is a plus.\nFamiliarity with Git or other version-control systems.\nKey Attributes\nStrong learning mindset and curiosity about semiconductor technologies.\nAttention to detail and commitment to quality.\nProblem-solving attitude with a willingness to learn from challenges.\nAbility to work effectively in a collaborative environment.\nPassion for innovation, automation, and continuous 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