{"id":2570171,"url":"https://alion.io/job/tylsemi-principal-engineer-static-timing-analysis-sta","title":"Principal Engineer – Static Timing Analysis (STA)","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":92,"open_postings":13,"ghost_share":0,"stale_share":0.308,"repost_share":0,"time_to_fill_p50_days":58,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":["IN"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":45000,"period":"year","method":"role_seniority_country_cell","sample_n":15},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"OpenAI","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-06-10T07:34:33Z","employer_posted_date":"2026-06-10","last_verified_at":"2026-10-28T11:09:54Z","board_verified":true,"closed_at":null,"days_open":140,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":139},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe areseekinga highly experienced Principal Engineer - STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deepexpertisein static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology nodes.1\nWhatYou’llDo\nLead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs.\nDrive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios. \nDefine timing constraints, validate SDCs, and ensure robust timingmethodologyexecution. \nCollaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence. \nAnalyze and resolve complex timing violations and critical path bottlenecks. \nSupport ECO implementation and signoff verification for advanced node tape-outs. \nDevelop and improve automation flows, scripts, timing dashboards, andmethodologyenhancements. \nMentor engineers and lead technical reviews for timing architecture and signoff readiness. \nWhatWe’reLooking For\n12+ years of experience in STA and timing signoff for ASIC/SOC programs.\nBachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field. \nStrongexpertisein setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques. \nHands-on experience with SynopsysPrimeTime, Tempus,StarRC, and related signoff tools. \nStrong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects. \nExperience with advanced technology nodes such as 7nm, 5nm, or below. \nStrong scripting skills inTcl, Python, Perl, or Shell scripting. \nExcellent technical leadership, debugging, communication, and stakeholder management skills. \nGood to Have\nExperience with package-aware timing analysis and chiplet architectures. \nExposure toAI/ML-driven timing optimization methodologies. \nFamiliarity with automotive or high-reliability SOC design standards. \nSuccess in This Role Looks Like\nSuccessful timing closure and signoff delivery for complex SOC tape-outs. \nEfficient management of timing convergence with minimal ECO impact. \nImproved STAmethodologyscalability, automation, and execution efficiency. \nStrong technical influence, mentoring contribution, and cross-functional leadership.","description_format":"text","description_chars":5635,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["AI Chips & Accelerators","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-14T22:44:48Z"}],"visa":[],"liveness":{"score":19,"band":"cold","label":"Long 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