{"id":2570174,"url":"https://alion.io/job/tylsemi-principal-physical-design-engineer","title":"Principal Physical Design Engineer","company":{"id":4380397,"name":"TYLsemi","domain":"tylsemi.ai","url":"https://alion.io/company/tylsemi","size_band":"501-1000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Rippling","truth_index":{"grade":"A","score":92,"open_postings":12,"ghost_share":0,"stale_share":0.333,"repost_share":0,"time_to_fill_p50_days":58,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":["IN"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":45000,"period":"year","method":"role_seniority_country_cell","sample_n":15},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Ansys RedHawk","optional":true},{"name":"OpenAI","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-06-10T07:39:08Z","employer_posted_date":"2026-06-10","last_verified_at":"2026-10-29T07:39:58Z","board_verified":true,"closed_at":null,"days_open":141,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":140},"description":"About TYLsemi, Inc.\nThe Opportunity\nThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?\nThat's what we solve. TYLsemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.\nThis isn't a nice-to-have. It's the critical path.\nWhy Now\nThe Market Window\nThe semiconductor industry is going through its biggest architectural shift in 40 years:\nMoore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.\nCustom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.\nIO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.\nTranslation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.\nCulture & Team: How We Work\nNo Politics, No Bureaucracy\nThere are no layers, no approval chains, no corporate theater.\nIf you have an idea, we test it. If it works, we ship it.\nNo endless meetings, no PowerPoint presentations to convince middle management.\nRemote-Friendly, Global Team\nUS team: Bay Area preferred, but we hire the best people regardless of location\nIndia team: Building a world-class design center in Bangalore\nMove Fast, Ship Real Products\nWe're not a research project. We have paying customers, committed capital, and aggressive timelines.\nThis is a company, not a lifestyle business. We're building to win.\nWhat We Value\nOwnership mindset. You're not here to execute someone else's roadmap. You're here to define it.\nBias for action. We move fast. Analysis paralysis doesn't fly here.\nDeep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.\nLow ego, high standards. We don't care about titles or politics. We care about results.\nThe Ask\nIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.\nWe're asking you to walk away from that and bet on us.\nHere's why you should:\nThe market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.\nThe team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.\nThe traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.\nThe work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.\nThis is the bet. Join us and build something that matters.\nOr stay comfortable. No judgment.\nBut if you're the kind of person who wants to take the shot, we'd love to talk.\nREADY TO JOIN?\nRole Overview\nWe areseekinga highly experienced Principal Physical Design Engineer to lead complex ASIC/SOC physical implementation activities across advanced technology nodes. The role requires deepexpertisein full-chip and block-level implementation, technical leadership in achieving best-in-class PPA (Power, Performance, Area), and ownership of high-quality tape-outs. The ideal candidate will collaborate closely with cross-functional teams and drivemethodologyimprovements, design closure strategies, and mentoring initiatives.1\nWhatYou’llDo\nLead end-to-end physical design implementation fromfloorplanningthrough GDSII signoff for complex SOCs and subsystems. \nDefine and drive implementation strategies for timing, congestion, power, area, IR/EM, and signal integrity closure. \nCollaborate with RTL, STA, DFT, Packaging, and CAD teams to resolve complex design and integration challenges. \nOwn physical signoff including timing, DRC, LVS, IR drop, EM, and reliability analysis. \nDrive advanced node implementation methodologies andoptimizedesignQoRacross multiple projects. \nDevelop and improve automation scripts, flows, and reusable methodologies for implementation efficiency. \nLead technical reviews, mentor junior engineers, andprovideproject execution guidance. \nSupport tape-out activities and customer/escalation debugging whenrequired. \nWhatWe’reLooking For\nBachelor’s orMaster’sdegree in Electronics, Electrical Engineering, VLSI, or related field. \n12+ years of hands-on experience in ASIC/SOC physical design implementation.\nStrongexpertiseinfloorplanning, placement, CTS, routing, timing closure, and physical verification.\nHands-on experience with EDA tools such as CadenceInnovus, Synopsys ICC2,PrimeTime,StarRC, andVoltus/RedHawk. \nDeep understanding of advanced node challenges including low-power design, SI, IR/EM, and variability analysis. \nProven experience delivering successful tape-outs at advanced technology nodes(7nm/5nm/3nm preferred).\nStrong scripting and automation skills usingTcl, Python, Perl, or Shell. \nExcellent problem-solving, leadership, communication, and stakeholder management skills. \nGood to Have\nExperience with hierarchical SOC integration and top-level implementation. \nExposure to 3D IC, chiplet, or package-aware implementation methodologies. \nExperienceinAI/ML-driven EDA optimization techniques. \nSuccess in This Role Looks Like\nSuccessful delivery of complex SOC designs meeting aggressive PPA and schedule targets. \nConsistent achievement of implementation and signoff closure with high-quality tape-outs. \nImproved team productivity throughmethodologyenhancements and automation. \nStrong technical leadership, mentoring impact, and cross-functional collaboration.","description_format":"text","description_chars":5835,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["AI Chips & Accelerators","Semiconductor IP & Chip Design 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